Eugeniy Paltsev 40db9367ec ARC: guard dsp early init against non ARCv2 ... As of today we guard early DSP init code with ARC_AUX_DSP_BUILD (0x7A) BCR check to verify that we have CPU with DSP configured. However that's not enough as in ARCv1 CPU the same BCR (0x7A) is used for checking MUL/MAC instructions presence. So, let's guard DSP early init against non ARCv2. Fixes: 4827d0cf74 ("ARC: handle DSP presence in HW") Reported-by: Angelo Ribeiro <angelor@synopsys.com> Suggested-by: Jose Abreu <oabreu@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2020-04-29 11:53:51 -07:00
..
boot	ARC updates for 5.7-rc1	2020-04-03 15:28:42 -07:00
configs	ARC: [plat-hsdk]: fix USB regression	2020-04-12 16:17:00 -07:00
include	ARC: guard dsp early init against non ARCv2	2020-04-29 11:53:51 -07:00
kernel	arc: remove #ifndef CONFIG_AS_CFI_SIGNAL_FRAME	2020-04-12 22:27:10 -07:00
lib	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
mm	mm: allow VM_FAULT_RETRY for multiple times	2020-04-02 09:35:30 -07:00
oprofile	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
plat-axs10x	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
plat-eznps	ARC: [plat-eznps]: Restrict to CONFIG_ISA_ARCOMPACT	2020-04-27 13:00:28 -07:00
plat-hsdk	ARC: [plat-hsdk]: allow to switch between AXI DMAC port configurations	2019-08-05 19:25:57 +05:30
plat-sim	ARC: merge HAPS-HS with nSIM-HS configs	2019-10-28 12:12:31 -07:00
plat-tb10x	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 333	2019-06-05 17:37:06 +02:00
Kbuild	treewide: Add SPDX license identifier - Kbuild	2019-05-30 11:32:33 -07:00
Kconfig	ARC: allow userspace DSP applications to use AGU extensions	2020-03-16 10:30:49 -07:00
Kconfig.debug	Kconfig: consolidate the "Kernel hacking" menu	2018-08-02 08:06:48 +09:00
Makefile	ARC: merge HAPS-HS with nSIM-HS configs	2019-10-28 12:12:31 -07:00