Lin Ming 40b7e05e17 perf, x86: Fix key indexing in Pentium-4 PMU ... Index 0-6 in p4_templates are reserved for common hardware events. So p4_templates is arranged as below: 0 - 6: common hardware events 7 - N: cache events N+1 - ...: other raw events Reported-by: Cyrill Gorcunov <gorcunov@openvz.org> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Acked-by: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Peter Zijlstra <peterz@infradead.org> LKML-Reference: <1268983738.13901.142.camel@minggr.sh.intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>		2010-03-19 09:23:17 +01:00
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asm	perf, x86: Fix key indexing in Pentium-4 PMU	2010-03-19 09:23:17 +01:00