forked from Minki/linux
6dedbd1d54
The TI K3 family of SoCs typically have one or more dual-core Arm Cortex R5F processor clusters/subsystems (R5FSS). This R5F subsystem/cluster can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - TCMA and TCMB (further interleaved into two banks). The subsystem does not have an MMU, but has a Region Address Translater (RAT) module that is accessible only from the R5Fs for providing translations between 32-bit CPU addresses into larger system bus addresses. Add a remoteproc driver to support this subsystem to be able to load and boot the R5F cores primarily in LockStep mode. The code also includes the base support for Split mode. Error Recovery and Power Management features are not currently supported. Loading support includes the internal TCMs and DDR. RAT support is left for a future patch, and as such the reserved memory carveout regions are all expected to be using memory regions within the first 2 GB. The R5F remote processors do not have an MMU, and so require fixed memory carveout regions matching the firmware image addresses. Support for this is provided by mandating multiple memory regions to be attached to the remoteproc device. The first memory region will be used to serve as the DMA pool for all dynamic allocations like the vrings and vring buffers. The remaining memory regions are mapped into the kernel at device probe time, and are used to provide address translations for firmware image segments without the need for any RSC_CARVEOUT entries. Any firmware image using memory outside of the supplied reserved memory carveout regions will be errored out. The R5F processors on TI K3 SoCs require a specific sequence for booting and shutting down the processors. This sequence is also dependent on the mode (LockStep or Split) the R5F cluster is configured for. The R5F cores have a Memory Protection Unit (MPU) that has a default configuration that does not allow the cores to run out of DDR out of reset. This is resolved by using the TCMs for boot-strapping code that applies the appropriate executable permissions on desired DDR memory. The loading into the TCMs requires that the resets be released first with the cores in halted state. The Power Sleep Controller (PSC) module on K3 SoCs requires that the cores be in WFI/WFE states with no active bus transactions before the cores can be put back into reset. Support for this is provided by using the newly introduced .prepare() and .unprepare() ops in the remoteproc core. The .prepare() ops is invoked before any loading, and the .unprepare() ops is invoked after the remoteproc resource cleanup. The R5F core resets are deasserted in .prepare() and asserted in .unprepare(), and the cores themselves are started and halted in .start() and .stop() ops. This ensures symmetric usage and allows the R5F cores state machine to be maintained properly between using the sysfs 'state' variable, bind/unbind and regular module load/unload flows. The subsystem is represented as a single remoteproc in LockStep mode, and as two remoteprocs in Split mode. The driver uses various TI-SCI interfaces to talk to the System Controller (DMSC) for managing configuration, power and reset management of these cores. IPC between the A53 cores and the R5 cores is supported through the virtio rpmsg stack using shared memory and OMAP Mailboxes. The AM65x SoCs typically have a single R5FSS in the MCU voltage domain. The J721E SoCs uses a slightly revised IP and typically have three R5FSSs, with one cluster present within the MCU voltage domain (MCU_R5FSS0), and the remaining two clusters present in the MAIN voltage domain (MAIN_R5FSS0 and MAIN_R5FSS1). The integration of these clusters on J721E SoC is also slightly different in that these IPs do support an actual local reset line, while they are a no-op on AM65x SoCs. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20201002234234.20704-3-s-anna@ti.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
37 lines
1.5 KiB
Makefile
37 lines
1.5 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Generic framework for controlling remote processors
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#
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obj-$(CONFIG_REMOTEPROC) += remoteproc.o
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remoteproc-y := remoteproc_core.o
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remoteproc-y += remoteproc_coredump.o
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remoteproc-y += remoteproc_debugfs.o
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remoteproc-y += remoteproc_sysfs.o
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remoteproc-y += remoteproc_virtio.o
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remoteproc-y += remoteproc_elf_loader.o
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obj-$(CONFIG_REMOTEPROC_CDEV) += remoteproc_cdev.o
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obj-$(CONFIG_IMX_REMOTEPROC) += imx_rproc.o
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obj-$(CONFIG_INGENIC_VPU_RPROC) += ingenic_rproc.o
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obj-$(CONFIG_MTK_SCP) += mtk_scp.o mtk_scp_ipi.o
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obj-$(CONFIG_OMAP_REMOTEPROC) += omap_remoteproc.o
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obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o
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obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o
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obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o
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obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o
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obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o
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obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o
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obj-$(CONFIG_QCOM_Q6V5_ADSP) += qcom_q6v5_adsp.o
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obj-$(CONFIG_QCOM_Q6V5_MSS) += qcom_q6v5_mss.o
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obj-$(CONFIG_QCOM_Q6V5_PAS) += qcom_q6v5_pas.o
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obj-$(CONFIG_QCOM_Q6V5_WCSS) += qcom_q6v5_wcss.o
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obj-$(CONFIG_QCOM_SYSMON) += qcom_sysmon.o
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obj-$(CONFIG_QCOM_WCNSS_PIL) += qcom_wcnss_pil.o
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qcom_wcnss_pil-y += qcom_wcnss.o
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qcom_wcnss_pil-y += qcom_wcnss_iris.o
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obj-$(CONFIG_ST_REMOTEPROC) += st_remoteproc.o
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obj-$(CONFIG_ST_SLIM_REMOTEPROC) += st_slim_rproc.o
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obj-$(CONFIG_STM32_RPROC) += stm32_rproc.o
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obj-$(CONFIG_TI_K3_DSP_REMOTEPROC) += ti_k3_dsp_remoteproc.o
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obj-$(CONFIG_TI_K3_R5_REMOTEPROC) += ti_k3_r5_remoteproc.o
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