Daniel Stuart 404be07f4e ASoC: intel: cht_bsw_max98090_ti: Add all Chromebooks that need pmc_plt_clk_0 quirk ... Every single baytrail chromebook sets PMC to 0, as can be seeing below by searching through coreboot source code: $ grep -rl "PMC_PLT_CLK\[0\]" . ./rambi/variants/glimmer/devicetree.cb ./rambi/variants/clapper/devicetree.cb ./rambi/variants/swanky/devicetree.cb ./rambi/variants/enguarde/devicetree.cb ./rambi/variants/winky/devicetree.cb ./rambi/variants/kip/devicetree.cb ./rambi/variants/squawks/devicetree.cb ./rambi/variants/orco/devicetree.cb ./rambi/variants/ninja/devicetree.cb ./rambi/variants/heli/devicetree.cb ./rambi/variants/sumo/devicetree.cb ./rambi/variants/banjo/devicetree.cb ./rambi/variants/candy/devicetree.cb ./rambi/variants/gnawty/devicetree.cb ./rambi/variants/rambi/devicetree.cb ./rambi/variants/quawks/devicetree.cb Plus, Cyan (only non-baytrail chromebook with max98090) also needs this patch for audio to work. Thus, this commit adds all the missing devices to bsw_max98090 quirk table, implemented by commit a182ecd380 ("ASoC: intel: cht_bsw_max98090_ti: Add quirk for boards using pmc_plt_clk_0"). Signed-off-by: Daniel Stuart <daniel.stuart14@gmail.com> Link: https://lore.kernel.org/r/20190815171300.30126-1-daniel.stuart14@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>		2019-08-20 14:12:06 +01:00
..
atom	Linux 5.2-rc6	2019-06-26 12:39:34 +01:00
baytrail	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
boards	ASoC: intel: cht_bsw_max98090_ti: Add all Chromebooks that need pmc_plt_clk_0 quirk	2019-08-20 14:12:06 +01:00
common	ASoC: Intel: Fix some acpi vs apci typo in somme comments	2019-07-26 13:09:30 +01:00
haswell	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
skylake	Linux 5.2-rc6	2019-06-26 12:39:34 +01:00
Kconfig	Linux 5.2-rc6	2019-06-26 12:39:34 +01:00
Makefile	ASoC: Intel: Fix Kconfig with top-level selector	2018-01-08 16:18:48 +00:00