forked from Minki/linux
3ffbba9511
xHCI needs to get a "Slot ID" from the host controller and allocate other data structures for every USB device. Make usb_alloc_dev() and usb_release_dev() allocate and free these device structures. After setting up the xHC device structures, usb_alloc_dev() must wait for the hardware to respond to an Enable Slot command. usb_alloc_dev() fires off a Disable Slot command and does not wait for it to complete. When the USB core wants to choose an address for the device, the xHCI driver must issue a Set Address command and wait for an event for that command. Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
492 lines
15 KiB
C
492 lines
15 KiB
C
/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "xhci.h"
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#define XHCI_INIT_VALUE 0x0
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/* Add verbose debugging later, just print everything for now */
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void xhci_dbg_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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xhci_dbg(xhci, "// xHCI capability registers at 0x%x:\n",
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(unsigned int) xhci->cap_regs);
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temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
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xhci_dbg(xhci, "// @%x = 0x%x (CAPLENGTH AND HCIVERSION)\n",
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(unsigned int) &xhci->cap_regs->hc_capbase,
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(unsigned int) temp);
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xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n",
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(unsigned int) HC_LENGTH(temp));
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#if 0
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xhci_dbg(xhci, "// HCIVERSION: 0x%x\n",
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(unsigned int) HC_VERSION(temp));
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#endif
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xhci_dbg(xhci, "// xHCI operational registers at 0x%x:\n",
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(unsigned int) xhci->op_regs);
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temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
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xhci_dbg(xhci, "// @%x = 0x%x RTSOFF\n",
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(unsigned int) &xhci->cap_regs->run_regs_off,
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(unsigned int) temp & RTSOFF_MASK);
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xhci_dbg(xhci, "// xHCI runtime registers at 0x%x:\n",
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(unsigned int) xhci->run_regs);
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temp = xhci_readl(xhci, &xhci->cap_regs->db_off);
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xhci_dbg(xhci, "// @%x = 0x%x DBOFF\n",
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(unsigned int) &xhci->cap_regs->db_off, temp);
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xhci_dbg(xhci, "// Doorbell array at 0x%x:\n",
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(unsigned int) xhci->dba);
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}
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void xhci_print_cap_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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xhci_dbg(xhci, "xHCI capability registers at 0x%x:\n",
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(unsigned int) xhci->cap_regs);
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temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
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xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
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(unsigned int) temp);
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xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
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(unsigned int) HC_LENGTH(temp));
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xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
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(unsigned int) HC_VERSION(temp));
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temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
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xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Max device slots: %u\n",
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(unsigned int) HCS_MAX_SLOTS(temp));
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xhci_dbg(xhci, " Max interrupters: %u\n",
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(unsigned int) HCS_MAX_INTRS(temp));
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xhci_dbg(xhci, " Max ports: %u\n",
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(unsigned int) HCS_MAX_PORTS(temp));
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temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
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xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Isoc scheduling threshold: %u\n",
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(unsigned int) HCS_IST(temp));
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xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n",
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(unsigned int) HCS_ERST_MAX(temp));
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temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
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xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n",
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(unsigned int) HCS_U1_LATENCY(temp));
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xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n",
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(unsigned int) HCS_U2_LATENCY(temp));
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temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
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xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
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xhci_dbg(xhci, " HC generates %s bit addresses\n",
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HCC_64BIT_ADDR(temp) ? "64" : "32");
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/* FIXME */
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xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n");
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temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
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xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
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}
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void xhci_print_command_reg(struct xhci_hcd *xhci)
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{
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u32 temp;
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temp = xhci_readl(xhci, &xhci->op_regs->command);
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xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
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xhci_dbg(xhci, " HC is %s\n",
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(temp & CMD_RUN) ? "running" : "being stopped");
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xhci_dbg(xhci, " HC has %sfinished hard reset\n",
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(temp & CMD_RESET) ? "not " : "");
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xhci_dbg(xhci, " Event Interrupts %s\n",
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(temp & CMD_EIE) ? "enabled " : "disabled");
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xhci_dbg(xhci, " Host System Error Interrupts %s\n",
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(temp & CMD_EIE) ? "enabled " : "disabled");
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xhci_dbg(xhci, " HC has %sfinished light reset\n",
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(temp & CMD_LRESET) ? "not " : "");
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}
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void xhci_print_status(struct xhci_hcd *xhci)
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{
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u32 temp;
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temp = xhci_readl(xhci, &xhci->op_regs->status);
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xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
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xhci_dbg(xhci, " Event ring is %sempty\n",
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(temp & STS_EINT) ? "not " : "");
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xhci_dbg(xhci, " %sHost System Error\n",
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(temp & STS_FATAL) ? "WARNING: " : "No ");
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xhci_dbg(xhci, " HC is %s\n",
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(temp & STS_HALT) ? "halted" : "running");
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}
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void xhci_print_op_regs(struct xhci_hcd *xhci)
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{
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xhci_dbg(xhci, "xHCI operational registers at 0x%x:\n",
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(unsigned int) xhci->op_regs);
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xhci_print_command_reg(xhci);
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xhci_print_status(xhci);
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}
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void xhci_print_ports(struct xhci_hcd *xhci)
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{
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u32 __iomem *addr;
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int i, j;
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int ports;
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char *names[NUM_PORT_REGS] = {
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"status",
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"power",
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"link",
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"reserved",
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};
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ports = HCS_MAX_PORTS(xhci->hcs_params1);
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addr = &xhci->op_regs->port_status_base;
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for (i = 0; i < ports; i++) {
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for (j = 0; j < NUM_PORT_REGS; ++j) {
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xhci_dbg(xhci, "0x%x port %s reg = 0x%x\n",
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(unsigned int) addr,
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names[j],
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(unsigned int) xhci_readl(xhci, addr));
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addr++;
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}
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}
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}
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void xhci_print_ir_set(struct xhci_hcd *xhci, struct intr_reg *ir_set, int set_num)
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{
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void *addr;
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u32 temp;
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addr = &ir_set->irq_pending;
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temp = xhci_readl(xhci, addr);
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if (temp == XHCI_INIT_VALUE)
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return;
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xhci_dbg(xhci, " 0x%x: ir_set[%i]\n", (unsigned int) ir_set, set_num);
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xhci_dbg(xhci, " 0x%x: ir_set.pending = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->irq_control;
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.control = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->erst_size;
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.erst_size = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->rsvd;
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temp = xhci_readl(xhci, addr);
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if (temp != XHCI_INIT_VALUE)
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xhci_dbg(xhci, " WARN: 0x%x: ir_set.rsvd = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->erst_base[0];
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.erst_base[0] = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->erst_base[1];
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.erst_base[1] = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->erst_dequeue[0];
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.erst_dequeue[0] = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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addr = &ir_set->erst_dequeue[1];
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temp = xhci_readl(xhci, addr);
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xhci_dbg(xhci, " 0x%x: ir_set.erst_dequeue[1] = 0x%x\n",
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(unsigned int) addr, (unsigned int) temp);
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}
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void xhci_print_run_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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int i;
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xhci_dbg(xhci, "xHCI runtime registers at 0x%x:\n",
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(unsigned int) xhci->run_regs);
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temp = xhci_readl(xhci, &xhci->run_regs->microframe_index);
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xhci_dbg(xhci, " 0x%x: Microframe index = 0x%x\n",
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(unsigned int) &xhci->run_regs->microframe_index,
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(unsigned int) temp);
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for (i = 0; i < 7; ++i) {
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temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]);
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if (temp != XHCI_INIT_VALUE)
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xhci_dbg(xhci, " WARN: 0x%x: Rsvd[%i] = 0x%x\n",
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(unsigned int) &xhci->run_regs->rsvd[i],
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i, (unsigned int) temp);
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}
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}
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void xhci_print_registers(struct xhci_hcd *xhci)
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{
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xhci_print_cap_regs(xhci);
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xhci_print_op_regs(xhci);
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xhci_print_ports(xhci);
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}
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void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
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{
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int i;
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for (i = 0; i < 4; ++i)
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xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
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i*4, trb->generic.field[i]);
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}
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/**
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* Debug a transfer request block (TRB).
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*/
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void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
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{
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u64 address;
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u32 type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK;
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switch (type) {
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case TRB_TYPE(TRB_LINK):
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xhci_dbg(xhci, "Link TRB:\n");
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xhci_print_trb_offsets(xhci, trb);
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address = trb->link.segment_ptr[0] +
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(((u64) trb->link.segment_ptr[1]) << 32);
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xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
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xhci_dbg(xhci, "Interrupter target = 0x%x\n",
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GET_INTR_TARGET(trb->link.intr_target));
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xhci_dbg(xhci, "Cycle bit = %u\n",
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(unsigned int) (trb->link.control & TRB_CYCLE));
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xhci_dbg(xhci, "Toggle cycle bit = %u\n",
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(unsigned int) (trb->link.control & LINK_TOGGLE));
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xhci_dbg(xhci, "No Snoop bit = %u\n",
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(unsigned int) (trb->link.control & TRB_NO_SNOOP));
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break;
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case TRB_TYPE(TRB_TRANSFER):
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address = trb->trans_event.buffer[0] +
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(((u64) trb->trans_event.buffer[1]) << 32);
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/*
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* FIXME: look at flags to figure out if it's an address or if
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* the data is directly in the buffer field.
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*/
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xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
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break;
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case TRB_TYPE(TRB_COMPLETION):
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address = trb->event_cmd.cmd_trb[0] +
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(((u64) trb->event_cmd.cmd_trb[1]) << 32);
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xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
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xhci_dbg(xhci, "Completion status = %u\n",
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(unsigned int) GET_COMP_CODE(trb->event_cmd.status));
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xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags);
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break;
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default:
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xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
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(unsigned int) type>>10);
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xhci_print_trb_offsets(xhci, trb);
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break;
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}
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}
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/**
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* Debug a segment with an xHCI ring.
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*
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* @return The Link TRB of the segment, or NULL if there is no Link TRB
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* (which is a bug, since all segments must have a Link TRB).
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*
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* Prints out all TRBs in the segment, even those after the Link TRB.
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*
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* XXX: should we print out TRBs that the HC owns? As long as we don't
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* write, that should be fine... We shouldn't expect that the memory pointed to
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* by the TRB is valid at all. Do we care about ones the HC owns? Probably,
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* for HC debugging.
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*/
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void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
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{
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int i;
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u32 addr = (u32) seg->dma;
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union xhci_trb *trb = seg->trbs;
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for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
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trb = &seg->trbs[i];
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xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr,
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(unsigned int) trb->link.segment_ptr[0],
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(unsigned int) trb->link.segment_ptr[1],
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(unsigned int) trb->link.intr_target,
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(unsigned int) trb->link.control);
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addr += sizeof(*trb);
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}
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}
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void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
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{
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xhci_dbg(xhci, "Ring deq = 0x%x (virt), 0x%x (dma)\n",
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(unsigned int) ring->dequeue,
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trb_virt_to_dma(ring->deq_seg, ring->dequeue));
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xhci_dbg(xhci, "Ring deq updated %u times\n",
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ring->deq_updates);
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xhci_dbg(xhci, "Ring enq = 0x%x (virt), 0x%x (dma)\n",
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(unsigned int) ring->enqueue,
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trb_virt_to_dma(ring->enq_seg, ring->enqueue));
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xhci_dbg(xhci, "Ring enq updated %u times\n",
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ring->enq_updates);
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}
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/**
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* Debugging for an xHCI ring, which is a queue broken into multiple segments.
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*
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* Print out each segment in the ring. Check that the DMA address in
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* each link segment actually matches the segment's stored DMA address.
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* Check that the link end bit is only set at the end of the ring.
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* Check that the dequeue and enqueue pointers point to real data in this ring
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* (not some other ring).
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*/
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void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
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{
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/* FIXME: Throw an error if any segment doesn't have a Link TRB */
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struct xhci_segment *seg;
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struct xhci_segment *first_seg = ring->first_seg;
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xhci_debug_segment(xhci, first_seg);
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if (!ring->enq_updates && !ring->deq_updates) {
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xhci_dbg(xhci, " Ring has not been updated\n");
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return;
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}
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for (seg = first_seg->next; seg != first_seg; seg = seg->next)
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xhci_debug_segment(xhci, seg);
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}
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void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
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{
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u32 addr = (u32) erst->erst_dma_addr;
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int i;
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struct xhci_erst_entry *entry;
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for (i = 0; i < erst->num_entries; ++i) {
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entry = &erst->entries[i];
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xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n",
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(unsigned int) addr,
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(unsigned int) entry->seg_addr[0],
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(unsigned int) entry->seg_addr[1],
|
|
(unsigned int) entry->seg_size,
|
|
(unsigned int) entry->rsvd);
|
|
addr += sizeof(*entry);
|
|
}
|
|
}
|
|
|
|
void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
|
|
{
|
|
u32 val;
|
|
|
|
val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[0]);
|
|
xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = 0x%x\n", val);
|
|
val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[1]);
|
|
xhci_dbg(xhci, "// xHC command ring deq ptr high bits = 0x%x\n", val);
|
|
}
|
|
|
|
void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_device_control *ctx, dma_addr_t dma, unsigned int last_ep)
|
|
{
|
|
int i, j;
|
|
int last_ep_ctx = 31;
|
|
/* Fields are 32 bits wide, DMA addresses are in bytes */
|
|
int field_size = 32 / 8;
|
|
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - drop flags\n",
|
|
(unsigned int) &ctx->drop_flags,
|
|
dma, ctx->drop_flags);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - add flags\n",
|
|
(unsigned int) &ctx->add_flags,
|
|
dma, ctx->add_flags);
|
|
dma += field_size;
|
|
for (i = 0; i > 6; ++i) {
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - rsvd[%d]\n",
|
|
(unsigned int) &ctx->rsvd[i],
|
|
dma, ctx->rsvd[i], i);
|
|
dma += field_size;
|
|
}
|
|
|
|
xhci_dbg(xhci, "Slot Context:\n");
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - dev_info\n",
|
|
(unsigned int) &ctx->slot.dev_info,
|
|
dma, ctx->slot.dev_info);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - dev_info2\n",
|
|
(unsigned int) &ctx->slot.dev_info2,
|
|
dma, ctx->slot.dev_info2);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - tt_info\n",
|
|
(unsigned int) &ctx->slot.tt_info,
|
|
dma, ctx->slot.tt_info);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - dev_state\n",
|
|
(unsigned int) &ctx->slot.dev_state,
|
|
dma, ctx->slot.dev_state);
|
|
dma += field_size;
|
|
for (i = 0; i > 4; ++i) {
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - rsvd[%d]\n",
|
|
(unsigned int) &ctx->slot.reserved[i],
|
|
dma, ctx->slot.reserved[i], i);
|
|
dma += field_size;
|
|
}
|
|
|
|
if (last_ep < 31)
|
|
last_ep_ctx = last_ep + 1;
|
|
for (i = 0; i < last_ep_ctx; ++i) {
|
|
xhci_dbg(xhci, "Endpoint %02d Context:\n", i);
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - ep_info\n",
|
|
(unsigned int) &ctx->ep[i].ep_info,
|
|
dma, ctx->ep[i].ep_info);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - ep_info2\n",
|
|
(unsigned int) &ctx->ep[i].ep_info2,
|
|
dma, ctx->ep[i].ep_info2);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - deq[0]\n",
|
|
(unsigned int) &ctx->ep[i].deq[0],
|
|
dma, ctx->ep[i].deq[0]);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - deq[1]\n",
|
|
(unsigned int) &ctx->ep[i].deq[1],
|
|
dma, ctx->ep[i].deq[1]);
|
|
dma += field_size;
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - tx_info\n",
|
|
(unsigned int) &ctx->ep[i].tx_info,
|
|
dma, ctx->ep[i].tx_info);
|
|
dma += field_size;
|
|
for (j = 0; j < 3; ++j) {
|
|
xhci_dbg(xhci, "@%08x (virt) @%08x (dma) %#08x - rsvd[%d]\n",
|
|
(unsigned int) &ctx->ep[i].reserved[j],
|
|
dma, ctx->ep[i].reserved[j], j);
|
|
dma += field_size;
|
|
}
|
|
}
|
|
}
|