forked from Minki/linux
584 lines
23 KiB
C
584 lines
23 KiB
C
#ifndef __NVIF_CLASS_H__
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#define __NVIF_CLASS_H__
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/*******************************************************************************
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* class identifiers
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******************************************************************************/
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/* the below match nvidia-assigned (either in hw, or sw) class numbers */
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#define NV_DEVICE 0x00000080
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#define NV_DMA_FROM_MEMORY 0x00000002
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#define NV_DMA_TO_MEMORY 0x00000003
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#define NV_DMA_IN_MEMORY 0x0000003d
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#define FERMI_TWOD_A 0x0000902d
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#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x0000903d
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#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
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#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
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#define NV04_DISP 0x00000046
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#define NV03_CHANNEL_DMA 0x0000006b
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#define NV10_CHANNEL_DMA 0x0000006e
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#define NV17_CHANNEL_DMA 0x0000176e
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#define NV40_CHANNEL_DMA 0x0000406e
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#define NV50_CHANNEL_DMA 0x0000506e
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#define G82_CHANNEL_DMA 0x0000826e
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#define NV50_CHANNEL_GPFIFO 0x0000506f
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#define G82_CHANNEL_GPFIFO 0x0000826f
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#define FERMI_CHANNEL_GPFIFO 0x0000906f
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#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
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#define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f
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#define NV50_DISP 0x00005070
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#define G82_DISP 0x00008270
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#define GT200_DISP 0x00008370
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#define GT214_DISP 0x00008570
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#define GT206_DISP 0x00008870
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#define GF110_DISP 0x00009070
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#define GK104_DISP 0x00009170
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#define GK110_DISP 0x00009270
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#define GM107_DISP 0x00009470
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#define GM204_DISP 0x00009570
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#define NV50_DISP_CURSOR 0x0000507a
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#define G82_DISP_CURSOR 0x0000827a
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#define GT214_DISP_CURSOR 0x0000857a
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#define GF110_DISP_CURSOR 0x0000907a
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#define GK104_DISP_CURSOR 0x0000917a
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#define NV50_DISP_OVERLAY 0x0000507b
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#define G82_DISP_OVERLAY 0x0000827b
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#define GT214_DISP_OVERLAY 0x0000857b
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#define GF110_DISP_OVERLAY 0x0000907b
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#define GK104_DISP_OVERLAY 0x0000917b
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#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c
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#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c
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#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c
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#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c
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#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c
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#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c
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#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c
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#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d
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#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d
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#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d
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#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d
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#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d
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#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d
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#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
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#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
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#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
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#define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d
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#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
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#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
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#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e
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#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e
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#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e
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#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e
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#define FERMI_A 0x00009097
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#define FERMI_B 0x00009197
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#define FERMI_C 0x00009297
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#define KEPLER_A 0x0000a097
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#define KEPLER_B 0x0000a197
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#define KEPLER_C 0x0000a297
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#define MAXWELL_A 0x0000b097
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#define MAXWELL_B 0x0000b197
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#define FERMI_COMPUTE_A 0x000090c0
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#define FERMI_COMPUTE_B 0x000091c0
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#define KEPLER_COMPUTE_A 0x0000a0c0
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#define KEPLER_COMPUTE_B 0x0000a1c0
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#define MAXWELL_COMPUTE_A 0x0000b0c0
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#define MAXWELL_COMPUTE_B 0x0000b1c0
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/*******************************************************************************
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* client
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******************************************************************************/
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#define NV_CLIENT_DEVLIST 0x00
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struct nv_client_devlist_v0 {
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__u8 version;
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__u8 count;
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__u8 pad02[6];
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__u64 device[];
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};
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/*******************************************************************************
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* device
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******************************************************************************/
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struct nv_device_v0 {
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__u8 version;
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__u8 pad01[7];
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__u64 device; /* device identifier, ~0 for client default */
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#define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL
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#define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL
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#define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL
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#define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL
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#define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL
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#define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL
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#define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL
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#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL
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#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL
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#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
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#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL
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#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
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#define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL
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#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL
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#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL
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#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
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#define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL
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#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL
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#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
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#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL
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#define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL
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__u64 disable; /* disable particular subsystems */
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__u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
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};
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#define NV_DEVICE_V0_INFO 0x00
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struct nv_device_info_v0 {
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__u8 version;
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#define NV_DEVICE_INFO_V0_IGP 0x00
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#define NV_DEVICE_INFO_V0_PCI 0x01
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#define NV_DEVICE_INFO_V0_AGP 0x02
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#define NV_DEVICE_INFO_V0_PCIE 0x03
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#define NV_DEVICE_INFO_V0_SOC 0x04
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__u8 platform;
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__u16 chipset; /* from NV_PMC_BOOT_0 */
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__u8 revision; /* from NV_PMC_BOOT_0 */
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#define NV_DEVICE_INFO_V0_TNT 0x01
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#define NV_DEVICE_INFO_V0_CELSIUS 0x02
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#define NV_DEVICE_INFO_V0_KELVIN 0x03
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#define NV_DEVICE_INFO_V0_RANKINE 0x04
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#define NV_DEVICE_INFO_V0_CURIE 0x05
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#define NV_DEVICE_INFO_V0_TESLA 0x06
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#define NV_DEVICE_INFO_V0_FERMI 0x07
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#define NV_DEVICE_INFO_V0_KEPLER 0x08
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#define NV_DEVICE_INFO_V0_MAXWELL 0x09
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__u8 family;
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__u8 pad06[2];
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__u64 ram_size;
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__u64 ram_user;
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};
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/*******************************************************************************
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* context dma
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******************************************************************************/
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struct nv_dma_v0 {
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__u8 version;
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#define NV_DMA_V0_TARGET_VM 0x00
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#define NV_DMA_V0_TARGET_VRAM 0x01
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#define NV_DMA_V0_TARGET_PCI 0x02
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#define NV_DMA_V0_TARGET_PCI_US 0x03
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#define NV_DMA_V0_TARGET_AGP 0x04
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__u8 target;
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#define NV_DMA_V0_ACCESS_VM 0x00
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#define NV_DMA_V0_ACCESS_RD 0x01
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#define NV_DMA_V0_ACCESS_WR 0x02
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#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
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__u8 access;
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__u8 pad03[5];
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__u64 start;
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__u64 limit;
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/* ... chipset-specific class data */
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};
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struct nv50_dma_v0 {
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__u8 version;
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#define NV50_DMA_V0_PRIV_VM 0x00
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#define NV50_DMA_V0_PRIV_US 0x01
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#define NV50_DMA_V0_PRIV__S 0x02
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__u8 priv;
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#define NV50_DMA_V0_PART_VM 0x00
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#define NV50_DMA_V0_PART_256 0x01
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#define NV50_DMA_V0_PART_1KB 0x02
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__u8 part;
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#define NV50_DMA_V0_COMP_NONE 0x00
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#define NV50_DMA_V0_COMP_1 0x01
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#define NV50_DMA_V0_COMP_2 0x02
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#define NV50_DMA_V0_COMP_VM 0x03
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__u8 comp;
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#define NV50_DMA_V0_KIND_PITCH 0x00
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#define NV50_DMA_V0_KIND_VM 0x7f
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__u8 kind;
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__u8 pad05[3];
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};
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struct gf100_dma_v0 {
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__u8 version;
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#define GF100_DMA_V0_PRIV_VM 0x00
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#define GF100_DMA_V0_PRIV_US 0x01
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#define GF100_DMA_V0_PRIV__S 0x02
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__u8 priv;
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#define GF100_DMA_V0_KIND_PITCH 0x00
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#define GF100_DMA_V0_KIND_VM 0xff
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__u8 kind;
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__u8 pad03[5];
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};
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struct gf110_dma_v0 {
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__u8 version;
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#define GF110_DMA_V0_PAGE_LP 0x00
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#define GF110_DMA_V0_PAGE_SP 0x01
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__u8 page;
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#define GF110_DMA_V0_KIND_PITCH 0x00
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#define GF110_DMA_V0_KIND_VM 0xff
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__u8 kind;
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__u8 pad03[5];
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};
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/*******************************************************************************
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* perfmon
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******************************************************************************/
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struct nvif_perfctr_v0 {
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__u8 version;
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__u8 pad01[1];
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__u16 logic_op;
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__u8 pad04[4];
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char name[4][64];
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};
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#define NVIF_PERFCTR_V0_QUERY 0x00
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#define NVIF_PERFCTR_V0_SAMPLE 0x01
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#define NVIF_PERFCTR_V0_READ 0x02
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struct nvif_perfctr_query_v0 {
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__u8 version;
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__u8 pad01[3];
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__u32 iter;
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char name[64];
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};
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struct nvif_perfctr_sample {
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};
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struct nvif_perfctr_read_v0 {
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__u8 version;
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__u8 pad01[7];
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__u32 ctr;
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__u32 clk;
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};
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/*******************************************************************************
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* device control
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******************************************************************************/
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#define NVIF_CONTROL_PSTATE_INFO 0x00
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#define NVIF_CONTROL_PSTATE_ATTR 0x01
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#define NVIF_CONTROL_PSTATE_USER 0x02
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struct nvif_control_pstate_info_v0 {
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__u8 version;
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__u8 count; /* out: number of power states */
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#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
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#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
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__s8 ustate_ac; /* out: target pstate index */
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__s8 ustate_dc; /* out: target pstate index */
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__s8 pwrsrc; /* out: current power source */
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#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
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#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
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__s8 pstate; /* out: current pstate index */
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__u8 pad06[2];
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};
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struct nvif_control_pstate_attr_v0 {
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__u8 version;
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#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
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__s8 state; /* in: index of pstate to query
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* out: pstate identifier
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*/
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__u8 index; /* in: index of attribute to query
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* out: index of next attribute, or 0 if no more
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*/
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__u8 pad03[5];
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__u32 min;
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__u32 max;
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char name[32];
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char unit[16];
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};
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struct nvif_control_pstate_user_v0 {
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__u8 version;
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#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
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#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
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__s8 ustate; /* in: pstate identifier */
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__s8 pwrsrc; /* in: target power source */
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__u8 pad03[5];
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};
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/*******************************************************************************
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* DMA FIFO channels
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******************************************************************************/
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struct nv03_channel_dma_v0 {
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__u8 version;
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__u8 chid;
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__u8 pad02[2];
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__u32 pushbuf;
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__u64 offset;
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};
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#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
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/*******************************************************************************
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* GPFIFO channels
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******************************************************************************/
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struct nv50_channel_gpfifo_v0 {
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__u8 version;
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__u8 chid;
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__u8 pad01[6];
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__u32 pushbuf;
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__u32 ilength;
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__u64 ioffset;
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};
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struct kepler_channel_gpfifo_a_v0 {
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__u8 version;
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
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__u8 engine;
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__u16 chid;
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__u8 pad04[4];
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__u32 pushbuf;
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__u32 ilength;
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__u64 ioffset;
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};
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/*******************************************************************************
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* legacy display
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******************************************************************************/
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#define NV04_DISP_NTFY_VBLANK 0x00
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#define NV04_DISP_NTFY_CONN 0x01
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struct nv04_disp_mthd_v0 {
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__u8 version;
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#define NV04_DISP_SCANOUTPOS 0x00
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__u8 method;
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__u8 head;
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__u8 pad03[5];
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};
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struct nv04_disp_scanoutpos_v0 {
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__u8 version;
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__u8 pad01[7];
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__s64 time[2];
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__u16 vblanks;
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__u16 vblanke;
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__u16 vtotal;
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__u16 vline;
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__u16 hblanks;
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__u16 hblanke;
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__u16 htotal;
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__u16 hline;
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};
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/*******************************************************************************
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* display
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******************************************************************************/
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#define NV50_DISP_MTHD 0x00
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struct nv50_disp_mthd_v0 {
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__u8 version;
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#define NV50_DISP_SCANOUTPOS 0x00
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__u8 method;
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__u8 head;
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__u8 pad03[5];
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};
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struct nv50_disp_mthd_v1 {
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__u8 version;
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#define NV50_DISP_MTHD_V1_DAC_PWR 0x10
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#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
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#define NV50_DISP_MTHD_V1_SOR_PWR 0x20
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#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
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#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
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#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
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#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
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#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
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__u8 method;
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__u16 hasht;
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__u16 hashm;
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__u8 pad06[2];
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};
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struct nv50_disp_dac_pwr_v0 {
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__u8 version;
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__u8 state;
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__u8 data;
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__u8 vsync;
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__u8 hsync;
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__u8 pad05[3];
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};
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struct nv50_disp_dac_load_v0 {
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__u8 version;
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__u8 load;
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__u8 pad02[2];
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__u32 data;
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};
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struct nv50_disp_sor_pwr_v0 {
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__u8 version;
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__u8 state;
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__u8 pad02[6];
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};
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struct nv50_disp_sor_hda_eld_v0 {
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__u8 version;
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__u8 pad01[7];
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__u8 data[];
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};
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struct nv50_disp_sor_hdmi_pwr_v0 {
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__u8 version;
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__u8 state;
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__u8 max_ac_packet;
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__u8 rekey;
|
|
__u8 pad04[4];
|
|
};
|
|
|
|
struct nv50_disp_sor_lvds_script_v0 {
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|
__u8 version;
|
|
__u8 pad01[1];
|
|
__u16 script;
|
|
__u8 pad04[4];
|
|
};
|
|
|
|
struct nv50_disp_sor_dp_pwr_v0 {
|
|
__u8 version;
|
|
__u8 state;
|
|
__u8 pad02[6];
|
|
};
|
|
|
|
struct nv50_disp_pior_pwr_v0 {
|
|
__u8 version;
|
|
__u8 state;
|
|
__u8 type;
|
|
__u8 pad03[5];
|
|
};
|
|
|
|
/* core */
|
|
struct nv50_disp_core_channel_dma_v0 {
|
|
__u8 version;
|
|
__u8 pad01[3];
|
|
__u32 pushbuf;
|
|
};
|
|
|
|
#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
|
|
|
|
/* cursor immediate */
|
|
struct nv50_disp_cursor_v0 {
|
|
__u8 version;
|
|
__u8 head;
|
|
__u8 pad02[6];
|
|
};
|
|
|
|
#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00
|
|
|
|
/* base */
|
|
struct nv50_disp_base_channel_dma_v0 {
|
|
__u8 version;
|
|
__u8 pad01[2];
|
|
__u8 head;
|
|
__u32 pushbuf;
|
|
};
|
|
|
|
#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
|
|
|
|
/* overlay */
|
|
struct nv50_disp_overlay_channel_dma_v0 {
|
|
__u8 version;
|
|
__u8 pad01[2];
|
|
__u8 head;
|
|
__u32 pushbuf;
|
|
};
|
|
|
|
#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
|
|
|
|
/* overlay immediate */
|
|
struct nv50_disp_overlay_v0 {
|
|
__u8 version;
|
|
__u8 head;
|
|
__u8 pad02[6];
|
|
};
|
|
|
|
#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00
|
|
|
|
/*******************************************************************************
|
|
* fermi
|
|
******************************************************************************/
|
|
|
|
#define FERMI_A_ZBC_COLOR 0x00
|
|
#define FERMI_A_ZBC_DEPTH 0x01
|
|
|
|
struct fermi_a_zbc_color_v0 {
|
|
__u8 version;
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c
|
|
#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40
|
|
__u8 format;
|
|
__u8 index;
|
|
__u8 pad03[5];
|
|
__u32 ds[4];
|
|
__u32 l2[4];
|
|
};
|
|
|
|
struct fermi_a_zbc_depth_v0 {
|
|
__u8 version;
|
|
#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01
|
|
__u8 format;
|
|
__u8 index;
|
|
__u8 pad03[5];
|
|
__u32 ds;
|
|
__u32 l2;
|
|
};
|
|
|
|
#endif
|