forked from Minki/linux
3f1be81eef
When the last CPU core in suspend, the CPU power rail can be turned off by setting flags to flow controller. Then the flow controller will inform PMC to turn off the CPU rail when the last CPU goes into suspend. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
345 lines
8.4 KiB
C
345 lines
8.4 KiB
C
/*
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* Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "flowctrl.h"
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#include "fuse.h"
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#include "pm.h"
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#include "pmc.h"
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#include "sleep.h"
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#define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
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#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
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#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
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#define PMC_CTRL 0x0
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#define PMC_CTRL_INTR_LOW (1 << 17)
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#define PMC_PWRGATE_TOGGLE 0x30
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#define PMC_PWRGATE_TOGGLE_START (1 << 8)
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#define PMC_REMOVE_CLAMPING 0x34
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#define PMC_PWRGATE_STATUS 0x38
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#define PMC_CPUPWRGOOD_TIMER 0xc8
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#define PMC_CPUPWROFF_TIMER 0xcc
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#define TEGRA_POWERGATE_PCIE 3
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#define TEGRA_POWERGATE_VDEC 4
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#define TEGRA_POWERGATE_CPU1 9
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#define TEGRA_POWERGATE_CPU2 10
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#define TEGRA_POWERGATE_CPU3 11
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static u8 tegra_cpu_domains[] = {
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0xFF, /* not available for CPU0 */
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TEGRA_POWERGATE_CPU1,
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TEGRA_POWERGATE_CPU2,
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TEGRA_POWERGATE_CPU3,
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};
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static DEFINE_SPINLOCK(tegra_powergate_lock);
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static void __iomem *tegra_pmc_base;
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static bool tegra_pmc_invert_interrupt;
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static struct clk *tegra_pclk;
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struct pmc_pm_data {
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u32 cpu_good_time; /* CPU power good time in uS */
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u32 cpu_off_time; /* CPU power off time in uS */
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u32 core_osc_time; /* Core power good osc time in uS */
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u32 core_pmu_time; /* Core power good pmu time in uS */
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u32 core_off_time; /* Core power off time in uS */
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bool corereq_high; /* Core power request active-high */
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bool sysclkreq_high; /* System clock request active-high */
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bool combined_req; /* Combined pwr req for CPU & Core */
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bool cpu_pwr_good_en; /* CPU power good signal is enabled */
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u32 lp0_vec_phy_addr; /* The phy addr of LP0 warm boot code */
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u32 lp0_vec_size; /* The size of LP0 warm boot code */
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enum tegra_suspend_mode suspend_mode;
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};
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static struct pmc_pm_data pmc_pm_data;
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static inline u32 tegra_pmc_readl(u32 reg)
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{
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return readl(tegra_pmc_base + reg);
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}
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static inline void tegra_pmc_writel(u32 val, u32 reg)
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{
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writel(val, tegra_pmc_base + reg);
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}
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static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
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{
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if (cpuid <= 0 || cpuid >= num_possible_cpus())
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return -EINVAL;
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return tegra_cpu_domains[cpuid];
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}
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static bool tegra_pmc_powergate_is_powered(int id)
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{
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return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
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}
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static int tegra_pmc_powergate_set(int id, bool new_state)
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{
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bool old_state;
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unsigned long flags;
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spin_lock_irqsave(&tegra_powergate_lock, flags);
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old_state = tegra_pmc_powergate_is_powered(id);
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WARN_ON(old_state == new_state);
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tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
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spin_unlock_irqrestore(&tegra_powergate_lock, flags);
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return 0;
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}
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static int tegra_pmc_powergate_remove_clamping(int id)
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{
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u32 mask;
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/*
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* Tegra has a bug where PCIE and VDE clamping masks are
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* swapped relatively to the partition ids.
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*/
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if (id == TEGRA_POWERGATE_VDEC)
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mask = (1 << TEGRA_POWERGATE_PCIE);
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else if (id == TEGRA_POWERGATE_PCIE)
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mask = (1 << TEGRA_POWERGATE_VDEC);
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else
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mask = (1 << id);
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tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
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return 0;
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}
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bool tegra_pmc_cpu_is_powered(int cpuid)
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{
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int id;
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id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
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if (id < 0)
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return false;
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return tegra_pmc_powergate_is_powered(id);
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}
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int tegra_pmc_cpu_power_on(int cpuid)
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{
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int id;
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id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
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if (id < 0)
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return id;
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return tegra_pmc_powergate_set(id, true);
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}
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int tegra_pmc_cpu_remove_clamping(int cpuid)
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{
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int id;
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id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
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if (id < 0)
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return id;
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return tegra_pmc_powergate_remove_clamping(id);
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}
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#ifdef CONFIG_PM_SLEEP
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static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
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{
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unsigned long long ticks;
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unsigned long long pclk;
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static unsigned long tegra_last_pclk;
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if (WARN_ON_ONCE(rate <= 0))
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pclk = 100000000;
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else
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pclk = rate;
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if ((rate != tegra_last_pclk)) {
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ticks = (us_on * pclk) + 999999ull;
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do_div(ticks, 1000000);
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tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
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ticks = (us_off * pclk) + 999999ull;
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do_div(ticks, 1000000);
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tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
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wmb();
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}
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tegra_last_pclk = pclk;
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}
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enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
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{
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return pmc_pm_data.suspend_mode;
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}
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void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
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{
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u32 reg, csr_reg;
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unsigned long rate = 0;
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reg = tegra_pmc_readl(PMC_CTRL);
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reg |= TEGRA_POWER_CPU_PWRREQ_OE;
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reg &= ~TEGRA_POWER_EFFECT_LP0;
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switch (tegra_chip_id) {
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case TEGRA20:
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case TEGRA30:
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break;
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default:
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/* Turn off CRAIL */
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csr_reg = flowctrl_read_cpu_csr(0);
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csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
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csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
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flowctrl_write_cpu_csr(0, csr_reg);
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break;
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}
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switch (mode) {
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case TEGRA_SUSPEND_LP2:
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rate = clk_get_rate(tegra_pclk);
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break;
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default:
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break;
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}
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set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
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rate);
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tegra_pmc_writel(reg, PMC_CTRL);
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}
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void tegra_pmc_suspend_init(void)
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{
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u32 reg;
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/* Always enable CPU power request */
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reg = tegra_pmc_readl(PMC_CTRL);
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reg |= TEGRA_POWER_CPU_PWRREQ_OE;
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tegra_pmc_writel(reg, PMC_CTRL);
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}
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#endif
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static const struct of_device_id matches[] __initconst = {
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{ .compatible = "nvidia,tegra114-pmc" },
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{ .compatible = "nvidia,tegra30-pmc" },
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{ .compatible = "nvidia,tegra20-pmc" },
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{ }
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};
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static void __init tegra_pmc_parse_dt(void)
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{
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struct device_node *np;
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u32 prop;
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enum tegra_suspend_mode suspend_mode;
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u32 core_good_time[2] = {0, 0};
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u32 lp0_vec[2] = {0, 0};
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np = of_find_matching_node(NULL, matches);
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BUG_ON(!np);
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tegra_pmc_base = of_iomap(np, 0);
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tegra_pmc_invert_interrupt = of_property_read_bool(np,
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"nvidia,invert-interrupt");
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tegra_pclk = of_clk_get_by_name(np, "pclk");
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WARN_ON(IS_ERR(tegra_pclk));
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/* Grabbing the power management configurations */
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if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
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suspend_mode = TEGRA_SUSPEND_NONE;
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} else {
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switch (prop) {
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case 0:
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suspend_mode = TEGRA_SUSPEND_LP0;
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break;
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case 1:
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suspend_mode = TEGRA_SUSPEND_LP1;
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break;
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case 2:
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suspend_mode = TEGRA_SUSPEND_LP2;
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break;
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default:
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suspend_mode = TEGRA_SUSPEND_NONE;
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break;
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}
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}
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suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
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if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
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suspend_mode = TEGRA_SUSPEND_NONE;
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pmc_pm_data.cpu_good_time = prop;
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if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
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suspend_mode = TEGRA_SUSPEND_NONE;
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pmc_pm_data.cpu_off_time = prop;
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if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
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core_good_time, ARRAY_SIZE(core_good_time)))
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suspend_mode = TEGRA_SUSPEND_NONE;
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pmc_pm_data.core_osc_time = core_good_time[0];
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pmc_pm_data.core_pmu_time = core_good_time[1];
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if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
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&prop))
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suspend_mode = TEGRA_SUSPEND_NONE;
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pmc_pm_data.core_off_time = prop;
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pmc_pm_data.corereq_high = of_property_read_bool(np,
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"nvidia,core-power-req-active-high");
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pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
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"nvidia,sys-clock-req-active-high");
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pmc_pm_data.combined_req = of_property_read_bool(np,
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"nvidia,combined-power-req");
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pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
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"nvidia,cpu-pwr-good-en");
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if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
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ARRAY_SIZE(lp0_vec)))
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if (suspend_mode == TEGRA_SUSPEND_LP0)
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suspend_mode = TEGRA_SUSPEND_LP1;
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pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
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pmc_pm_data.lp0_vec_size = lp0_vec[1];
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pmc_pm_data.suspend_mode = suspend_mode;
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}
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void __init tegra_pmc_init(void)
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{
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u32 val;
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tegra_pmc_parse_dt();
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val = tegra_pmc_readl(PMC_CTRL);
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if (tegra_pmc_invert_interrupt)
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val |= PMC_CTRL_INTR_LOW;
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else
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val &= ~PMC_CTRL_INTR_LOW;
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tegra_pmc_writel(val, PMC_CTRL);
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}
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