forked from Minki/linux
70bcc9ba15
Since PCIe is using SMMUv1 which only supports 15-bit stream ID, only 7-bit PCI bus id is used to specify stream ID. Therefore, we only limit the PCI bus range to 0x7f. Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
173 lines
4.1 KiB
Plaintext
173 lines
4.1 KiB
Plaintext
/*
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* DTS file for AMD Seattle SoC
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*
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* Copyright (C) 2014 Advanced Micro Devices, Inc.
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*/
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/ {
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compatible = "amd,seattle";
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interrupt-parent = <&gic0>;
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#address-cells = <2>;
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#size-cells = <2>;
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gic0: interrupt-controller@e1101000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x0 0xe1110000 0 0x1000>,
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<0x0 0xe112f000 0 0x2000>,
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<0x0 0xe1140000 0 0x10000>,
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<0x0 0xe1160000 0 0x10000>;
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interrupts = <1 9 0xf04>;
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ranges = <0 0 0 0xe1100000 0 0x100000>;
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v2m0: v2m@e0080000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0x00080000 0 0x1000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xff04>,
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<1 14 0xff04>,
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<1 11 0xff04>,
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<1 10 0xff04>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 7 4>,
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<0 8 4>,
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<0 9 4>,
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<0 10 4>,
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<0 11 4>,
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<0 12 4>,
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<0 13 4>,
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<0 14 4>;
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};
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smb0: smb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* DDR range is 40-bit addressing */
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dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
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/include/ "amd-seattle-clks.dtsi"
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sata0: sata@e0300000 {
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compatible = "snps,dwc-ahci";
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reg = <0 0xe0300000 0 0x800>;
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interrupts = <0 355 4>;
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clocks = <&sataclk_333mhz>;
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dma-coherent;
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};
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i2c0: i2c@e1000000 {
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status = "disabled";
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compatible = "snps,designware-i2c";
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reg = <0 0xe1000000 0 0x1000>;
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interrupts = <0 357 4>;
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clocks = <&uartspiclk_100mhz>;
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};
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serial0: serial@e1010000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0xe1010000 0 0x1000>;
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interrupts = <0 328 4>;
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clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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spi0: ssp@e1020000 {
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status = "disabled";
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compatible = "arm,pl022", "arm,primecell";
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#gpio-cells = <2>;
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reg = <0 0xe1020000 0 0x1000>;
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spi-controller;
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interrupts = <0 330 4>;
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clocks = <&uartspiclk_100mhz>;
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clock-names = "apb_pclk";
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};
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spi1: ssp@e1030000 {
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status = "disabled";
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compatible = "arm,pl022", "arm,primecell";
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#gpio-cells = <2>;
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reg = <0 0xe1030000 0 0x1000>;
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spi-controller;
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interrupts = <0 329 4>;
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clocks = <&uartspiclk_100mhz>;
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clock-names = "apb_pclk";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gpio0: gpio@e1040000 {
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status = "disabled";
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <2>;
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reg = <0 0xe1040000 0 0x1000>;
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gpio-controller;
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interrupts = <0 359 4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&uartspiclk_100mhz>;
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clock-names = "apb_pclk";
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};
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gpio1: gpio@e1050000 {
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status = "disabled";
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compatible = "arm,pl061", "arm,primecell";
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#gpio-cells = <2>;
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reg = <0 0xe1050000 0 0x1000>;
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gpio-controller;
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interrupts = <0 358 4>;
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clocks = <&uartspiclk_100mhz>;
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clock-names = "apb_pclk";
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};
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ccp0: ccp@e0100000 {
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status = "disabled";
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compatible = "amd,ccp-seattle-v1a";
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reg = <0 0xe0100000 0 0x10000>;
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interrupts = <0 3 4>;
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dma-coherent;
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};
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pcie0: pcie@f0000000 {
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compatible = "pci-host-ecam-generic";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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bus-range = <0 0x7f>;
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msi-parent = <&v2m0>;
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reg = <0 0xf0000000 0 0x10000000>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map =
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<0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
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<0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
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<0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
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<0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
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dma-coherent;
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dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
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ranges =
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/* I/O Memory (size=64K) */
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<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
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/* 32-bit MMIO (size=2G) */
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<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
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/* 64-bit MMIO (size= 124G) */
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<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
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};
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};
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};
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