forked from Minki/linux
3e648cbeb3
Change the nx-842 common driver to wait for loading of both platform drivers, and fail loading if the platform driver pointer is not set. Add an independent platform driver pointer, that the platform drivers set if they find they are able to load (i.e. if they find their platform devicetree node(s)). The problem is currently, the main nx-842 driver will stay loaded even if there is no platform driver and thus no possible way it can do any compression or decompression. This allows the crypto 842-nx driver to load even if it won't actually work. For crypto compression users (e.g. zswap) that expect an available crypto compression driver to actually work, this is bad. This patch fixes that, so the 842-nx crypto compression driver won't load if it doesn't have the driver and hardware available to perform the compression. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
128 lines
3.9 KiB
C
128 lines
3.9 KiB
C
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#ifndef __NX_842_H__
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#define __NX_842_H__
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/nx842.h>
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#include <linux/sw842.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/ratelimit.h>
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/* Restrictions on Data Descriptor List (DDL) and Entry (DDE) buffers
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*
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* From NX P8 workbook, sec 4.9.1 "842 details"
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* Each DDE buffer is 128 byte aligned
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* Each DDE buffer size is a multiple of 32 bytes (except the last)
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* The last DDE buffer size is a multiple of 8 bytes
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*/
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#define DDE_BUFFER_ALIGN (128)
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#define DDE_BUFFER_SIZE_MULT (32)
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#define DDE_BUFFER_LAST_MULT (8)
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/* Arbitrary DDL length limit
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* Allows max buffer size of MAX-1 to MAX pages
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* (depending on alignment)
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*/
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#define DDL_LEN_MAX (17)
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/* CCW 842 CI/FC masks
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* NX P8 workbook, section 4.3.1, figure 4-6
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* "CI/FC Boundary by NX CT type"
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*/
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#define CCW_CI_842 (0x00003ff8)
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#define CCW_FC_842 (0x00000007)
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/* CCW Function Codes (FC) for 842
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* NX P8 workbook, section 4.9, table 4-28
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* "Function Code Definitions for 842 Memory Compression"
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*/
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#define CCW_FC_842_COMP_NOCRC (0)
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#define CCW_FC_842_COMP_CRC (1)
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#define CCW_FC_842_DECOMP_NOCRC (2)
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#define CCW_FC_842_DECOMP_CRC (3)
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#define CCW_FC_842_MOVE (4)
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/* CSB CC Error Types for 842
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* NX P8 workbook, section 4.10.3, table 4-30
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* "Reported Error Types Summary Table"
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*/
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/* These are all duplicates of existing codes defined in icswx.h. */
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#define CSB_CC_TRANSLATION_DUP1 (80)
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#define CSB_CC_TRANSLATION_DUP2 (82)
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#define CSB_CC_TRANSLATION_DUP3 (84)
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#define CSB_CC_TRANSLATION_DUP4 (86)
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#define CSB_CC_TRANSLATION_DUP5 (92)
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#define CSB_CC_TRANSLATION_DUP6 (94)
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#define CSB_CC_PROTECTION_DUP1 (81)
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#define CSB_CC_PROTECTION_DUP2 (83)
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#define CSB_CC_PROTECTION_DUP3 (85)
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#define CSB_CC_PROTECTION_DUP4 (87)
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#define CSB_CC_PROTECTION_DUP5 (93)
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#define CSB_CC_PROTECTION_DUP6 (95)
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#define CSB_CC_RD_EXTERNAL_DUP1 (89)
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#define CSB_CC_RD_EXTERNAL_DUP2 (90)
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#define CSB_CC_RD_EXTERNAL_DUP3 (91)
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/* These are specific to NX */
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/* 842 codes */
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#define CSB_CC_TPBC_GT_SPBC (64) /* no error, but >1 comp ratio */
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#define CSB_CC_CRC_MISMATCH (65) /* decomp crc mismatch */
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#define CSB_CC_TEMPL_INVALID (66) /* decomp invalid template value */
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#define CSB_CC_TEMPL_OVERFLOW (67) /* decomp template shows data after end */
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/* sym crypt codes */
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#define CSB_CC_DECRYPT_OVERFLOW (64)
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/* asym crypt codes */
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#define CSB_CC_MINV_OVERFLOW (128)
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/* These are reserved for hypervisor use */
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#define CSB_CC_HYP_RESERVE_START (240)
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#define CSB_CC_HYP_RESERVE_END (253)
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#define CSB_CC_HYP_NO_HW (254)
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#define CSB_CC_HYP_HANG_ABORTED (255)
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/* CCB Completion Modes (CM) for 842
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* NX P8 workbook, section 4.3, figure 4-5
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* "CRB Details - Normal Cop_Req (CL=00, C=1)"
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*/
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#define CCB_CM_EXTRA_WRITE (CCB_CM0_ALL_COMPLETIONS & CCB_CM12_STORE)
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#define CCB_CM_INTERRUPT (CCB_CM0_ALL_COMPLETIONS & CCB_CM12_INTERRUPT)
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#define LEN_ON_PAGE(pa) (PAGE_SIZE - ((pa) & ~PAGE_MASK))
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static inline unsigned long nx842_get_pa(void *addr)
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{
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if (!is_vmalloc_addr(addr))
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return __pa(addr);
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return page_to_phys(vmalloc_to_page(addr)) + offset_in_page(addr);
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}
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/* Get/Set bit fields */
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#define MASK_LSH(m) (__builtin_ffsl(m) - 1)
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#define GET_FIELD(v, m) (((v) & (m)) >> MASK_LSH(m))
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#define SET_FIELD(v, m, val) (((v) & ~(m)) | (((val) << MASK_LSH(m)) & (m)))
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struct nx842_driver {
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char *name;
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struct module *owner;
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struct nx842_constraints *constraints;
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int (*compress)(const unsigned char *in, unsigned int in_len,
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unsigned char *out, unsigned int *out_len,
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void *wrkmem);
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int (*decompress)(const unsigned char *in, unsigned int in_len,
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unsigned char *out, unsigned int *out_len,
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void *wrkmem);
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};
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struct nx842_driver *nx842_platform_driver(void);
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bool nx842_platform_driver_set(struct nx842_driver *driver);
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void nx842_platform_driver_unset(struct nx842_driver *driver);
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bool nx842_platform_driver_get(void);
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void nx842_platform_driver_put(void);
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#endif /* __NX_842_H__ */
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