..
dcn10_cm_common.c
dcn10_cm_common.h
dcn10_dpp_cm.c
dcn10_dpp_dscl.c
drm/amd/display: fix function scopes
2021-12-13 16:34:26 -05:00
dcn10_dpp.c
drm/amd/display: fix function scopes
2021-12-13 16:34:26 -05:00
dcn10_dpp.h
drm/amd/display: Remove the repeated dpp1_full_bypass declaration
2021-06-18 17:14:36 -04:00
dcn10_dwb.c
dcn10_dwb.h
dcn10_hubbub.c
drm/amd/display: Add support for SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616.
2021-05-27 15:00:47 -04:00
dcn10_hubbub.h
drm/amd/display: remove compbuf size wait
2021-07-21 13:39:25 -04:00
dcn10_hubp.c
drm/amd/display: log additional register state for debug
2021-07-21 13:39:25 -04:00
dcn10_hubp.h
drm/amd/display: log additional register state for debug
2021-07-21 13:39:25 -04:00
dcn10_hw_sequencer_debug.c
dcn10_hw_sequencer_debug.h
dcn10_hw_sequencer.c
drm/amd/display: Remove unused variable
2022-02-23 14:03:20 -05:00
dcn10_hw_sequencer.h
drm/amd/display: Refactor visual confirm
2021-06-08 12:18:37 -04:00
dcn10_init.c
drm/amd/display: Added power down for DCN10
2021-12-30 08:54:44 -05:00
dcn10_init.h
dcn10_ipp.c
dcn10_ipp.h
drm/amd/display: add cyan_skillfish display support
2021-10-04 15:22:57 -04:00
dcn10_link_encoder.c
drm/amd/display: add set dp lane settings to link_hwss
2022-02-02 18:26:32 -05:00
dcn10_link_encoder.h
drm/amd/display: add set dp lane settings to link_hwss
2022-02-02 18:26:32 -05:00
dcn10_mpc.c
drm/amd/display: Refactor visual confirm
2021-06-08 12:18:37 -04:00
dcn10_mpc.h
dcn10_opp.c
drm/amd/display: fix function scopes
2021-12-13 16:34:26 -05:00
dcn10_opp.h
dcn10_optc.c
drm/amd/display: fix function scopes
2021-12-13 16:34:26 -05:00
dcn10_optc.h
drm/amd/display: log additional register state for debug
2021-07-21 13:39:25 -04:00
dcn10_resource.c
drm/amd/display: fix function scopes
2021-12-13 16:34:26 -05:00
dcn10_resource.h
dcn10_stream_encoder.c
drm/amd/display: revert "Reset fifo after enable otg"
2022-02-02 18:26:31 -05:00
dcn10_stream_encoder.h
drm/amd/display: revert "Reset fifo after enable otg"
2022-02-02 18:26:31 -05:00
Makefile