Thomas Daniel 3e5b6f05a2 drm/i915: Reset logical ring contexts' head and tail during GPU reset ... Work was getting left behind in LRC contexts during reset. This causes a hang if the GPU is reset when HEAD==TAIL because the context's ringbuffer head and tail don't get reset and retiring a request doesn't alter them, so the ring still appears full. Added a function intel_lr_context_reset() to reset head and tail on a LRC and its ringbuffer. Call intel_lr_context_reset() for each context in i915_gem_context_reset() when in execlists mode. Testcase: igt/pm_rps --run-subtest reset #bdw Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88096 Signed-off-by: Thomas Daniel <thomas.daniel@intel.com> Reviewed-by: Dave Gordon <david.s.gordon@intel.com> [danvet: Flatten control flow in the lrc reset code a notch.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2015-02-24 00:19:37 +01:00
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drm	drm/i915: Reset logical ring contexts' head and tail during GPU reset	2015-02-24 00:19:37 +01:00
host1x	gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register	2014-11-13 16:11:57 +01:00
ipu-v3	gpu: ipu-di: Switch to DIV_ROUND_CLOSEST for DI clock divider calc	2015-01-07 19:15:04 +01:00
vga
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