forked from Minki/linux
b69416b51b
This driver is now limited to just doing the basic clock board and FHC chip initialization and registering the platform devices for the per-board LEDs, which are driven by the new LEDS_STARFIRE driver. The IRQ register handling is already confined purely to the device tree code. Signed-off-by: David S. Miller <davem@davemloft.net>
675 lines
20 KiB
C
675 lines
20 KiB
C
/*
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* sbus.c: UltraSparc SBUS controller support.
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*
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* Copyright (C) 1999 David S. Miller (davem@redhat.com)
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/upa.h>
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#include <asm/cache.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/oplib.h>
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#include <asm/starfire.h>
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#include "iommu_common.h"
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#define MAP_BASE ((u32)0xc0000000)
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/* Offsets from iommu_regs */
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#define SYSIO_IOMMUREG_BASE 0x2400UL
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#define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
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#define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
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#define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
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#define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
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#define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
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#define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
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#define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
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#define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
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#define IOMMU_DRAM_VALID (1UL << 30UL)
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/* Offsets from strbuf_regs */
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#define SYSIO_STRBUFREG_BASE 0x2800UL
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#define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
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#define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
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#define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
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#define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
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#define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
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#define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
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#define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
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#define STRBUF_TAG_VALID 0x02UL
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/* Enable 64-bit DVMA mode for the given device. */
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void sbus_set_sbus64(struct device *dev, int bursts)
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{
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struct iommu *iommu = dev->archdata.iommu;
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struct of_device *op = to_of_device(dev);
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const struct linux_prom_registers *regs;
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unsigned long cfg_reg;
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int slot;
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u64 val;
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regs = of_get_property(op->node, "reg", NULL);
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if (!regs) {
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printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %s\n",
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op->node->full_name);
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return;
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}
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slot = regs->which_io;
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cfg_reg = iommu->write_complete_reg;
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switch (slot) {
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case 0:
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cfg_reg += 0x20UL;
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break;
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case 1:
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cfg_reg += 0x28UL;
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break;
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case 2:
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cfg_reg += 0x30UL;
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break;
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case 3:
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cfg_reg += 0x38UL;
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break;
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case 13:
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cfg_reg += 0x40UL;
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break;
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case 14:
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cfg_reg += 0x48UL;
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break;
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case 15:
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cfg_reg += 0x50UL;
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break;
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default:
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return;
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};
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val = upa_readq(cfg_reg);
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if (val & (1UL << 14UL)) {
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/* Extended transfer mode already enabled. */
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return;
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}
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val |= (1UL << 14UL);
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if (bursts & DMA_BURST8)
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val |= (1UL << 1UL);
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if (bursts & DMA_BURST16)
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val |= (1UL << 2UL);
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if (bursts & DMA_BURST32)
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val |= (1UL << 3UL);
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if (bursts & DMA_BURST64)
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val |= (1UL << 4UL);
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upa_writeq(val, cfg_reg);
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}
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/* INO number to IMAP register offset for SYSIO external IRQ's.
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* This should conform to both Sunfire/Wildfire server and Fusion
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* desktop designs.
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*/
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#define SYSIO_IMAP_SLOT0 0x2c00UL
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#define SYSIO_IMAP_SLOT1 0x2c08UL
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#define SYSIO_IMAP_SLOT2 0x2c10UL
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#define SYSIO_IMAP_SLOT3 0x2c18UL
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#define SYSIO_IMAP_SCSI 0x3000UL
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#define SYSIO_IMAP_ETH 0x3008UL
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#define SYSIO_IMAP_BPP 0x3010UL
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#define SYSIO_IMAP_AUDIO 0x3018UL
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#define SYSIO_IMAP_PFAIL 0x3020UL
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#define SYSIO_IMAP_KMS 0x3028UL
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#define SYSIO_IMAP_FLPY 0x3030UL
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#define SYSIO_IMAP_SHW 0x3038UL
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#define SYSIO_IMAP_KBD 0x3040UL
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#define SYSIO_IMAP_MS 0x3048UL
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#define SYSIO_IMAP_SER 0x3050UL
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#define SYSIO_IMAP_TIM0 0x3060UL
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#define SYSIO_IMAP_TIM1 0x3068UL
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#define SYSIO_IMAP_UE 0x3070UL
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#define SYSIO_IMAP_CE 0x3078UL
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#define SYSIO_IMAP_SBERR 0x3080UL
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#define SYSIO_IMAP_PMGMT 0x3088UL
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#define SYSIO_IMAP_GFX 0x3090UL
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#define SYSIO_IMAP_EUPA 0x3098UL
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#define bogon ((unsigned long) -1)
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static unsigned long sysio_irq_offsets[] = {
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/* SBUS Slot 0 --> 3, level 1 --> 7 */
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SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
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SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
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SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
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SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
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SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
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SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
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SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
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SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
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/* Onboard devices (not relevant/used on SunFire). */
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SYSIO_IMAP_SCSI,
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SYSIO_IMAP_ETH,
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SYSIO_IMAP_BPP,
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bogon,
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SYSIO_IMAP_AUDIO,
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SYSIO_IMAP_PFAIL,
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bogon,
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bogon,
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SYSIO_IMAP_KMS,
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SYSIO_IMAP_FLPY,
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SYSIO_IMAP_SHW,
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SYSIO_IMAP_KBD,
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SYSIO_IMAP_MS,
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SYSIO_IMAP_SER,
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bogon,
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bogon,
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SYSIO_IMAP_TIM0,
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SYSIO_IMAP_TIM1,
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bogon,
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bogon,
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SYSIO_IMAP_UE,
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SYSIO_IMAP_CE,
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SYSIO_IMAP_SBERR,
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SYSIO_IMAP_PMGMT,
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};
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#undef bogon
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#define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
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/* Convert Interrupt Mapping register pointer to associated
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* Interrupt Clear register pointer, SYSIO specific version.
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*/
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#define SYSIO_ICLR_UNUSED0 0x3400UL
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#define SYSIO_ICLR_SLOT0 0x3408UL
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#define SYSIO_ICLR_SLOT1 0x3448UL
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#define SYSIO_ICLR_SLOT2 0x3488UL
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#define SYSIO_ICLR_SLOT3 0x34c8UL
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static unsigned long sysio_imap_to_iclr(unsigned long imap)
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{
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unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
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return imap + diff;
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}
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static unsigned int sbus_build_irq(struct of_device *op, unsigned int ino)
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{
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struct iommu *iommu = op->dev.archdata.iommu;
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unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
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unsigned long imap, iclr;
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int sbus_level = 0;
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imap = sysio_irq_offsets[ino];
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if (imap == ((unsigned long)-1)) {
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prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
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ino);
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prom_halt();
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}
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imap += reg_base;
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/* SYSIO inconsistency. For external SLOTS, we have to select
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* the right ICLR register based upon the lower SBUS irq level
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* bits.
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*/
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if (ino >= 0x20) {
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iclr = sysio_imap_to_iclr(imap);
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} else {
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int sbus_slot = (ino & 0x18)>>3;
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sbus_level = ino & 0x7;
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switch(sbus_slot) {
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case 0:
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iclr = reg_base + SYSIO_ICLR_SLOT0;
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break;
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case 1:
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iclr = reg_base + SYSIO_ICLR_SLOT1;
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break;
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case 2:
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iclr = reg_base + SYSIO_ICLR_SLOT2;
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break;
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default:
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case 3:
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iclr = reg_base + SYSIO_ICLR_SLOT3;
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break;
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};
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iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
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}
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return build_irq(sbus_level, iclr, imap);
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}
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/* Error interrupt handling. */
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#define SYSIO_UE_AFSR 0x0030UL
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#define SYSIO_UE_AFAR 0x0038UL
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#define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
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#define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
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#define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
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#define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
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#define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
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#define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
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#define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
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#define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */
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#define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
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#define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
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#define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
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static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
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{
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struct of_device *op = dev_id;
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struct iommu *iommu = op->dev.archdata.iommu;
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unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
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unsigned long afsr_reg, afar_reg;
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unsigned long afsr, afar, error_bits;
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int reported, portid;
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afsr_reg = reg_base + SYSIO_UE_AFSR;
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afar_reg = reg_base + SYSIO_UE_AFAR;
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/* Latch error status. */
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afsr = upa_readq(afsr_reg);
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afar = upa_readq(afar_reg);
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/* Clear primary/secondary error status bits. */
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error_bits = afsr &
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(SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
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SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
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upa_writeq(error_bits, afsr_reg);
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portid = of_getintprop_default(op->node, "portid", -1);
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/* Log the error. */
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printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
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portid,
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(((error_bits & SYSIO_UEAFSR_PPIO) ?
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"PIO" :
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((error_bits & SYSIO_UEAFSR_PDRD) ?
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"DVMA Read" :
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((error_bits & SYSIO_UEAFSR_PDWR) ?
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"DVMA Write" : "???")))));
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printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
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portid,
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(afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
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(afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
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(afsr & SYSIO_UEAFSR_MID) >> 37UL);
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printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
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printk("SYSIO[%x]: Secondary UE errors [", portid);
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reported = 0;
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if (afsr & SYSIO_UEAFSR_SPIO) {
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reported++;
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printk("(PIO)");
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}
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if (afsr & SYSIO_UEAFSR_SDRD) {
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reported++;
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printk("(DVMA Read)");
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}
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if (afsr & SYSIO_UEAFSR_SDWR) {
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reported++;
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printk("(DVMA Write)");
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}
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if (!reported)
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printk("(none)");
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printk("]\n");
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return IRQ_HANDLED;
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}
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#define SYSIO_CE_AFSR 0x0040UL
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#define SYSIO_CE_AFAR 0x0048UL
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#define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
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#define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
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#define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
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#define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
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#define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
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#define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
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#define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
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#define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
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#define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
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#define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
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#define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
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#define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
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static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
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{
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struct of_device *op = dev_id;
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struct iommu *iommu = op->dev.archdata.iommu;
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unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
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unsigned long afsr_reg, afar_reg;
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unsigned long afsr, afar, error_bits;
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int reported, portid;
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afsr_reg = reg_base + SYSIO_CE_AFSR;
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afar_reg = reg_base + SYSIO_CE_AFAR;
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/* Latch error status. */
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afsr = upa_readq(afsr_reg);
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afar = upa_readq(afar_reg);
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/* Clear primary/secondary error status bits. */
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error_bits = afsr &
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(SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
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SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
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upa_writeq(error_bits, afsr_reg);
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portid = of_getintprop_default(op->node, "portid", -1);
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printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
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portid,
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(((error_bits & SYSIO_CEAFSR_PPIO) ?
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"PIO" :
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((error_bits & SYSIO_CEAFSR_PDRD) ?
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"DVMA Read" :
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((error_bits & SYSIO_CEAFSR_PDWR) ?
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"DVMA Write" : "???")))));
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/* XXX Use syndrome and afar to print out module string just like
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* XXX UDB CE trap handler does... -DaveM
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*/
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printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
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portid,
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(afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
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(afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
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(afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
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(afsr & SYSIO_CEAFSR_MID) >> 37UL);
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printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
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printk("SYSIO[%x]: Secondary CE errors [", portid);
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reported = 0;
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if (afsr & SYSIO_CEAFSR_SPIO) {
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reported++;
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printk("(PIO)");
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}
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if (afsr & SYSIO_CEAFSR_SDRD) {
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reported++;
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printk("(DVMA Read)");
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}
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if (afsr & SYSIO_CEAFSR_SDWR) {
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reported++;
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printk("(DVMA Write)");
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}
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if (!reported)
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printk("(none)");
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printk("]\n");
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return IRQ_HANDLED;
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}
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#define SYSIO_SBUS_AFSR 0x2010UL
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#define SYSIO_SBUS_AFAR 0x2018UL
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#define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */
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#define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
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#define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
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#define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */
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#define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
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#define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
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#define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */
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#define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */
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#define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */
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#define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */
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#define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */
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#define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
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static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
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{
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struct of_device *op = dev_id;
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struct iommu *iommu = op->dev.archdata.iommu;
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unsigned long afsr_reg, afar_reg, reg_base;
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unsigned long afsr, afar, error_bits;
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int reported, portid;
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reg_base = iommu->write_complete_reg - 0x2000UL;
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afsr_reg = reg_base + SYSIO_SBUS_AFSR;
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afar_reg = reg_base + SYSIO_SBUS_AFAR;
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afsr = upa_readq(afsr_reg);
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afar = upa_readq(afar_reg);
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/* Clear primary/secondary error status bits. */
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error_bits = afsr &
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(SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
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SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
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upa_writeq(error_bits, afsr_reg);
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portid = of_getintprop_default(op->node, "portid", -1);
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/* Log the error. */
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printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
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portid,
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(((error_bits & SYSIO_SBAFSR_PLE) ?
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"Late PIO Error" :
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((error_bits & SYSIO_SBAFSR_PTO) ?
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"Time Out" :
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((error_bits & SYSIO_SBAFSR_PBERR) ?
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"Error Ack" : "???")))),
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(afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
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printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
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portid,
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(afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
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(afsr & SYSIO_SBAFSR_MID) >> 37UL);
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printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
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printk("SYSIO[%x]: Secondary SBUS errors [", portid);
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reported = 0;
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if (afsr & SYSIO_SBAFSR_SLE) {
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reported++;
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printk("(Late PIO Error)");
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}
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if (afsr & SYSIO_SBAFSR_STO) {
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reported++;
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printk("(Time Out)");
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}
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if (afsr & SYSIO_SBAFSR_SBERR) {
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reported++;
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printk("(Error Ack)");
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}
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if (!reported)
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printk("(none)");
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printk("]\n");
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/* XXX check iommu/strbuf for further error status XXX */
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return IRQ_HANDLED;
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}
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#define ECC_CONTROL 0x0020UL
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#define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */
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#define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */
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#define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */
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#define SYSIO_UE_INO 0x34
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#define SYSIO_CE_INO 0x35
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#define SYSIO_SBUSERR_INO 0x36
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static void __init sysio_register_error_handlers(struct of_device *op)
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{
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struct iommu *iommu = op->dev.archdata.iommu;
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unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
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unsigned int irq;
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u64 control;
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int portid;
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portid = of_getintprop_default(op->node, "portid", -1);
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irq = sbus_build_irq(op, SYSIO_UE_INO);
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if (request_irq(irq, sysio_ue_handler, 0,
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"SYSIO_UE", op) < 0) {
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prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
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portid);
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prom_halt();
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}
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irq = sbus_build_irq(op, SYSIO_CE_INO);
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if (request_irq(irq, sysio_ce_handler, 0,
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"SYSIO_CE", op) < 0) {
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prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
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portid);
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prom_halt();
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}
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irq = sbus_build_irq(op, SYSIO_SBUSERR_INO);
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if (request_irq(irq, sysio_sbus_error_handler, 0,
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"SYSIO_SBERR", op) < 0) {
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prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
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portid);
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prom_halt();
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}
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/* Now turn the error interrupts on and also enable ECC checking. */
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upa_writeq((SYSIO_ECNTRL_ECCEN |
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SYSIO_ECNTRL_UEEN |
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SYSIO_ECNTRL_CEEN),
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reg_base + ECC_CONTROL);
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control = upa_readq(iommu->write_complete_reg);
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control |= 0x100UL; /* SBUS Error Interrupt Enable */
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upa_writeq(control, iommu->write_complete_reg);
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}
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/* Boot time initialization. */
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static void __init sbus_iommu_init(struct of_device *op)
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{
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const struct linux_prom64_registers *pr;
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struct device_node *dp = op->node;
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struct iommu *iommu;
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struct strbuf *strbuf;
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unsigned long regs, reg_base;
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int i, portid;
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u64 control;
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pr = of_get_property(dp, "reg", NULL);
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if (!pr) {
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prom_printf("sbus_iommu_init: Cannot map SYSIO "
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"control registers.\n");
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prom_halt();
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}
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regs = pr->phys_addr;
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iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
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if (!iommu)
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goto fatal_memory_error;
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strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC);
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if (!strbuf)
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goto fatal_memory_error;
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op->dev.archdata.iommu = iommu;
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op->dev.archdata.stc = strbuf;
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op->dev.archdata.numa_node = -1;
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reg_base = regs + SYSIO_IOMMUREG_BASE;
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iommu->iommu_control = reg_base + IOMMU_CONTROL;
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iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE;
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iommu->iommu_flush = reg_base + IOMMU_FLUSH;
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iommu->iommu_tags = iommu->iommu_control +
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(IOMMU_TAGDIAG - IOMMU_CONTROL);
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reg_base = regs + SYSIO_STRBUFREG_BASE;
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strbuf->strbuf_control = reg_base + STRBUF_CONTROL;
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strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH;
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strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC;
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strbuf->strbuf_enabled = 1;
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strbuf->strbuf_flushflag = (volatile unsigned long *)
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((((unsigned long)&strbuf->__flushflag_buf[0])
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+ 63UL)
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& ~63UL);
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strbuf->strbuf_flushflag_pa = (unsigned long)
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__pa(strbuf->strbuf_flushflag);
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/* The SYSIO SBUS control register is used for dummy reads
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* in order to ensure write completion.
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*/
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iommu->write_complete_reg = regs + 0x2000UL;
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portid = of_getintprop_default(op->node, "portid", -1);
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printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n",
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portid, regs);
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/* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
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if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
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goto fatal_memory_error;
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control = upa_readq(iommu->iommu_control);
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control = ((7UL << 16UL) |
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(0UL << 2UL) |
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(1UL << 1UL) |
|
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(1UL << 0UL));
|
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upa_writeq(control, iommu->iommu_control);
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/* Clean out any cruft in the IOMMU using
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* diagnostic accesses.
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*/
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for (i = 0; i < 16; i++) {
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unsigned long dram, tag;
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|
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dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL);
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tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
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|
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dram += (unsigned long)i * 8UL;
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tag += (unsigned long)i * 8UL;
|
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upa_writeq(0, dram);
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upa_writeq(0, tag);
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}
|
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upa_readq(iommu->write_complete_reg);
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|
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/* Give the TSB to SYSIO. */
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upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
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|
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/* Setup streaming buffer, DE=1 SB_EN=1 */
|
|
control = (1UL << 1UL) | (1UL << 0UL);
|
|
upa_writeq(control, strbuf->strbuf_control);
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|
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/* Clear out the tags using diagnostics. */
|
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for (i = 0; i < 16; i++) {
|
|
unsigned long ptag, ltag;
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|
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ptag = strbuf->strbuf_control +
|
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(STRBUF_PTAGDIAG - STRBUF_CONTROL);
|
|
ltag = strbuf->strbuf_control +
|
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(STRBUF_LTAGDIAG - STRBUF_CONTROL);
|
|
ptag += (unsigned long)i * 8UL;
|
|
ltag += (unsigned long)i * 8UL;
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|
|
upa_writeq(0UL, ptag);
|
|
upa_writeq(0UL, ltag);
|
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}
|
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|
|
/* Enable DVMA arbitration for all devices/slots. */
|
|
control = upa_readq(iommu->write_complete_reg);
|
|
control |= 0x3fUL;
|
|
upa_writeq(control, iommu->write_complete_reg);
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|
|
/* Now some Xfire specific grot... */
|
|
if (this_is_starfire)
|
|
starfire_hookup(portid);
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|
|
sysio_register_error_handlers(op);
|
|
return;
|
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|
|
fatal_memory_error:
|
|
prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
|
|
}
|
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|
|
static int __init sbus_init(void)
|
|
{
|
|
struct device_node *dp;
|
|
|
|
for_each_node_by_name(dp, "sbus") {
|
|
struct of_device *op = of_find_device_by_node(dp);
|
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|
|
sbus_iommu_init(op);
|
|
of_propagate_archdata(op);
|
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}
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|
|
return 0;
|
|
}
|
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|
|
subsys_initcall(sbus_init);
|