forked from Minki/linux
cbda94e039
These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUz/1+GCrR//JCVInAQJmfg/9GyqHatDjjUPUBjUQRIEtKgGdmQwdbDqF x+OrS/q5B5zYbpIWkbkt1IUYJfU+89Z5ev9jxI4rV824Nu9Y92mHPDnv+N/ptkIh q2OVP3bQDpWs3aEVV2B1HBNcWrNUuwco9BJu05eegEePii/cto0/wKwWIgUmrmjy xOLthsnp2YmeplGs7ctC6Dz8XbmELebpawejTGylARXei/SwmzB/YYDgJbYjRL2I WSCVa8Vo+MZaGC/yxdKVTtvsKVQenxGoMO3ojikJeRdvuVRJds48Cw+UBdzWYNeJ 3Ssvbdx6Xltf9jy/7H0btOUgxPetZuUV+2XpbWfGu0Zr9FcGDv3q9hrxA+UYKnkY GIGU0otSsmpHnX5Ms3E2xnHiV/fihxA3qohqts5kYRBDr5uc+IpW6SbDymQliCGG OO4XmIVM3pmsqAqP3Zuseemt9CeSW2yC0XlfXkzjO74yY39c+WLBbtGI40Z5W6i0 mM1C8RD3QSNijYCEC8eqz06BQfRImsPs+jllsnJTZaHfbOsib718uvandjfG26lN 616YMcqq0Sp51HIQ4qW7f2dQr7vOyNqbukdkrwF5JgkY/nVki5kdciRg/yeipRy6 Ey80a+OTq0GQljM0F2dcH/A1eHH9KsuI1L6NdSMJsl0h6guIBORPTwTw3qJ13OkR wpJyM+Gm+Fk= =u/FI -----END PGP SIGNATURE----- Merge tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver changes from Arnd Bergmann: "These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable" * tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac." Revert "net: stmmac: Add SOCFPGA glue driver" ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks ARM: STi: Add reset controller support to mach-sti Kconfig drivers: reset: stih416: add softreset controller drivers: reset: stih415: add softreset controller drivers: reset: Reset controller driver for STiH416 drivers: reset: Reset controller driver for STiH415 drivers: reset: STi SoC system configuration reset controller support dts: socfpga: Add sysmgr node so the gmac can use to reference dts: socfpga: Add support for SD/MMC on the SOCFPGA platform reset: Add optional resets and stubs ARM: shmobile: r7s72100: fix bus clock calculation Power: Reset: Generalize qnap-poweroff to work on Synology devices. dts: socfpga: Update clock entry to support multiple parents ARM: socfpga: Update socfpga_defconfig dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. net: stmmac: Add SOCFPGA glue driver watchdog: orion_wdt: Use %pa to print 'phys_addr_t' drivers: cci: Export CCI PMU revision ...
307 lines
8.8 KiB
C
307 lines
8.8 KiB
C
/*
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* rtc-isl12057 - Driver for Intersil ISL12057 I2C Real Time Clock
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*
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* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
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*
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* This work is largely based on Intersil ISL1208 driver developed by
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* Hebert Valerio Riedel <hvr@gnu.org>.
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*
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* Detailed datasheet on which this development is based is available here:
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*
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* http://natisbad.org/NAS2/refs/ISL12057.pdf
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/rtc.h>
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#include <linux/i2c.h>
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#include <linux/bcd.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#define DRV_NAME "rtc-isl12057"
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/* RTC section */
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#define ISL12057_REG_RTC_SC 0x00 /* Seconds */
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#define ISL12057_REG_RTC_MN 0x01 /* Minutes */
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#define ISL12057_REG_RTC_HR 0x02 /* Hours */
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#define ISL12057_REG_RTC_HR_PM BIT(5) /* AM/PM bit in 12h format */
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#define ISL12057_REG_RTC_HR_MIL BIT(6) /* 24h/12h format */
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#define ISL12057_REG_RTC_DW 0x03 /* Day of the Week */
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#define ISL12057_REG_RTC_DT 0x04 /* Date */
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#define ISL12057_REG_RTC_MO 0x05 /* Month */
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#define ISL12057_REG_RTC_YR 0x06 /* Year */
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#define ISL12057_RTC_SEC_LEN 7
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/* Alarm 1 section */
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#define ISL12057_REG_A1_SC 0x07 /* Alarm 1 Seconds */
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#define ISL12057_REG_A1_MN 0x08 /* Alarm 1 Minutes */
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#define ISL12057_REG_A1_HR 0x09 /* Alarm 1 Hours */
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#define ISL12057_REG_A1_HR_PM BIT(5) /* AM/PM bit in 12h format */
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#define ISL12057_REG_A1_HR_MIL BIT(6) /* 24h/12h format */
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#define ISL12057_REG_A1_DWDT 0x0A /* Alarm 1 Date / Day of the week */
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#define ISL12057_REG_A1_DWDT_B BIT(6) /* DW / DT selection bit */
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#define ISL12057_A1_SEC_LEN 4
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/* Alarm 2 section */
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#define ISL12057_REG_A2_MN 0x0B /* Alarm 2 Minutes */
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#define ISL12057_REG_A2_HR 0x0C /* Alarm 2 Hours */
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#define ISL12057_REG_A2_DWDT 0x0D /* Alarm 2 Date / Day of the week */
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#define ISL12057_A2_SEC_LEN 3
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/* Control/Status registers */
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#define ISL12057_REG_INT 0x0E
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#define ISL12057_REG_INT_A1IE BIT(0) /* Alarm 1 interrupt enable bit */
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#define ISL12057_REG_INT_A2IE BIT(1) /* Alarm 2 interrupt enable bit */
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#define ISL12057_REG_INT_INTCN BIT(2) /* Interrupt control enable bit */
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#define ISL12057_REG_INT_RS1 BIT(3) /* Freq out control bit 1 */
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#define ISL12057_REG_INT_RS2 BIT(4) /* Freq out control bit 2 */
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#define ISL12057_REG_INT_EOSC BIT(7) /* Oscillator enable bit */
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#define ISL12057_REG_SR 0x0F
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#define ISL12057_REG_SR_A1F BIT(0) /* Alarm 1 interrupt bit */
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#define ISL12057_REG_SR_A2F BIT(1) /* Alarm 2 interrupt bit */
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#define ISL12057_REG_SR_OSF BIT(7) /* Oscillator failure bit */
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/* Register memory map length */
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#define ISL12057_MEM_MAP_LEN 0x10
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struct isl12057_rtc_data {
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struct regmap *regmap;
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struct mutex lock;
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};
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static void isl12057_rtc_regs_to_tm(struct rtc_time *tm, u8 *regs)
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{
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tm->tm_sec = bcd2bin(regs[ISL12057_REG_RTC_SC]);
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tm->tm_min = bcd2bin(regs[ISL12057_REG_RTC_MN]);
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if (regs[ISL12057_REG_RTC_HR] & ISL12057_REG_RTC_HR_MIL) { /* AM/PM */
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tm->tm_hour = bcd2bin(regs[ISL12057_REG_RTC_HR] & 0x0f);
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if (regs[ISL12057_REG_RTC_HR] & ISL12057_REG_RTC_HR_PM)
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tm->tm_hour += 12;
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} else { /* 24 hour mode */
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tm->tm_hour = bcd2bin(regs[ISL12057_REG_RTC_HR] & 0x3f);
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}
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tm->tm_mday = bcd2bin(regs[ISL12057_REG_RTC_DT]);
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tm->tm_wday = bcd2bin(regs[ISL12057_REG_RTC_DW]) - 1; /* starts at 1 */
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tm->tm_mon = bcd2bin(regs[ISL12057_REG_RTC_MO]) - 1; /* starts at 1 */
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tm->tm_year = bcd2bin(regs[ISL12057_REG_RTC_YR]) + 100;
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}
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static int isl12057_rtc_tm_to_regs(u8 *regs, struct rtc_time *tm)
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{
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/*
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* The clock has an 8 bit wide bcd-coded register for the year.
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* tm_year is an offset from 1900 and we are interested in the
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* 2000-2099 range, so any value less than 100 is invalid.
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*/
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if (tm->tm_year < 100)
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return -EINVAL;
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regs[ISL12057_REG_RTC_SC] = bin2bcd(tm->tm_sec);
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regs[ISL12057_REG_RTC_MN] = bin2bcd(tm->tm_min);
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regs[ISL12057_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
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regs[ISL12057_REG_RTC_DT] = bin2bcd(tm->tm_mday);
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regs[ISL12057_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
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regs[ISL12057_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
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regs[ISL12057_REG_RTC_DW] = bin2bcd(tm->tm_wday + 1);
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return 0;
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}
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/*
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* Try and match register bits w/ fixed null values to see whether we
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* are dealing with an ISL12057. Note: this function is called early
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* during init and hence does need mutex protection.
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*/
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static int isl12057_i2c_validate_chip(struct regmap *regmap)
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{
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u8 regs[ISL12057_MEM_MAP_LEN];
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static const u8 mask[ISL12057_MEM_MAP_LEN] = { 0x80, 0x80, 0x80, 0xf8,
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0xc0, 0x60, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x60, 0x7c };
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int ret, i;
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ret = regmap_bulk_read(regmap, 0, regs, ISL12057_MEM_MAP_LEN);
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if (ret)
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return ret;
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for (i = 0; i < ISL12057_MEM_MAP_LEN; ++i) {
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if (regs[i] & mask[i]) /* check if bits are cleared */
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return -ENODEV;
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}
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return 0;
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}
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static int isl12057_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct isl12057_rtc_data *data = dev_get_drvdata(dev);
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u8 regs[ISL12057_RTC_SEC_LEN];
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int ret;
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mutex_lock(&data->lock);
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ret = regmap_bulk_read(data->regmap, ISL12057_REG_RTC_SC, regs,
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ISL12057_RTC_SEC_LEN);
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mutex_unlock(&data->lock);
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if (ret) {
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dev_err(dev, "%s: RTC read failed\n", __func__);
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return ret;
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}
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isl12057_rtc_regs_to_tm(tm, regs);
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return rtc_valid_tm(tm);
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}
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static int isl12057_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct isl12057_rtc_data *data = dev_get_drvdata(dev);
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u8 regs[ISL12057_RTC_SEC_LEN];
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int ret;
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ret = isl12057_rtc_tm_to_regs(regs, tm);
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if (ret)
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return ret;
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mutex_lock(&data->lock);
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ret = regmap_bulk_write(data->regmap, ISL12057_REG_RTC_SC, regs,
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ISL12057_RTC_SEC_LEN);
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mutex_unlock(&data->lock);
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if (ret)
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dev_err(dev, "%s: RTC write failed\n", __func__);
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return ret;
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}
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/*
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* Check current RTC status and enable/disable what needs to be. Return 0 if
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* everything went ok and a negative value upon error. Note: this function
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* is called early during init and hence does need mutex protection.
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*/
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static int isl12057_check_rtc_status(struct device *dev, struct regmap *regmap)
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{
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int ret;
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/* Enable oscillator if not already running */
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ret = regmap_update_bits(regmap, ISL12057_REG_INT,
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ISL12057_REG_INT_EOSC, 0);
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if (ret < 0) {
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dev_err(dev, "Unable to enable oscillator\n");
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return ret;
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}
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/* Clear oscillator failure bit if needed */
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ret = regmap_update_bits(regmap, ISL12057_REG_SR,
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ISL12057_REG_SR_OSF, 0);
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if (ret < 0) {
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dev_err(dev, "Unable to clear oscillator failure bit\n");
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return ret;
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}
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/* Clear alarm bit if needed */
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ret = regmap_update_bits(regmap, ISL12057_REG_SR,
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ISL12057_REG_SR_A1F, 0);
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if (ret < 0) {
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dev_err(dev, "Unable to clear alarm bit\n");
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return ret;
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}
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return 0;
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}
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static const struct rtc_class_ops rtc_ops = {
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.read_time = isl12057_rtc_read_time,
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.set_time = isl12057_rtc_set_time,
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};
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static struct regmap_config isl12057_rtc_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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};
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static int isl12057_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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struct device *dev = &client->dev;
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struct isl12057_rtc_data *data;
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struct rtc_device *rtc;
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struct regmap *regmap;
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int ret;
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if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
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I2C_FUNC_SMBUS_BYTE_DATA |
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I2C_FUNC_SMBUS_I2C_BLOCK))
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return -ENODEV;
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regmap = devm_regmap_init_i2c(client, &isl12057_rtc_regmap_config);
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if (IS_ERR(regmap)) {
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ret = PTR_ERR(regmap);
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dev_err(dev, "regmap allocation failed: %d\n", ret);
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return ret;
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}
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ret = isl12057_i2c_validate_chip(regmap);
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if (ret)
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return ret;
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ret = isl12057_check_rtc_status(dev, regmap);
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if (ret)
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return ret;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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mutex_init(&data->lock);
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data->regmap = regmap;
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dev_set_drvdata(dev, data);
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rtc = devm_rtc_device_register(dev, DRV_NAME, &rtc_ops, THIS_MODULE);
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return PTR_ERR_OR_ZERO(rtc);
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}
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#ifdef CONFIG_OF
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static struct of_device_id isl12057_dt_match[] = {
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{ .compatible = "isl,isl12057" },
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{ },
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};
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#endif
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static const struct i2c_device_id isl12057_id[] = {
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{ "isl12057", 0 },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, isl12057_id);
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static struct i2c_driver isl12057_driver = {
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(isl12057_dt_match),
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},
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.probe = isl12057_probe,
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.id_table = isl12057_id,
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};
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module_i2c_driver(isl12057_driver);
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MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>");
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MODULE_DESCRIPTION("Intersil ISL12057 RTC driver");
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MODULE_LICENSE("GPL");
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