forked from Minki/linux
3cf080a7b7
The condition checking allowed key length was invalid. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Tadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
640 lines
17 KiB
C
640 lines
17 KiB
C
/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/module.h>
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#include <crypto/internal/rsa.h>
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#include <crypto/internal/akcipher.h>
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#include <crypto/akcipher.h>
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#include <linux/dma-mapping.h>
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#include <linux/fips.h>
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#include "qat_rsakey-asn1.h"
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#include "icp_qat_fw_pke.h"
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#include "adf_accel_devices.h"
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#include "adf_transport.h"
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#include "adf_common_drv.h"
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#include "qat_crypto.h"
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struct qat_rsa_input_params {
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union {
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struct {
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dma_addr_t m;
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dma_addr_t e;
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dma_addr_t n;
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} enc;
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struct {
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dma_addr_t c;
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dma_addr_t d;
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dma_addr_t n;
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} dec;
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u64 in_tab[8];
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};
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} __packed __aligned(64);
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struct qat_rsa_output_params {
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union {
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struct {
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dma_addr_t c;
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} enc;
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struct {
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dma_addr_t m;
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} dec;
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u64 out_tab[8];
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};
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} __packed __aligned(64);
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struct qat_rsa_ctx {
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char *n;
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char *e;
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char *d;
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dma_addr_t dma_n;
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dma_addr_t dma_e;
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dma_addr_t dma_d;
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unsigned int key_sz;
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struct qat_crypto_instance *inst;
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} __packed __aligned(64);
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struct qat_rsa_request {
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struct qat_rsa_input_params in;
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struct qat_rsa_output_params out;
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dma_addr_t phy_in;
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dma_addr_t phy_out;
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char *src_align;
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struct icp_qat_fw_pke_request req;
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struct qat_rsa_ctx *ctx;
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int err;
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} __aligned(64);
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static void qat_rsa_cb(struct icp_qat_fw_pke_resp *resp)
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{
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struct akcipher_request *areq = (void *)(__force long)resp->opaque;
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struct qat_rsa_request *req = PTR_ALIGN(akcipher_request_ctx(areq), 64);
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struct device *dev = &GET_DEV(req->ctx->inst->accel_dev);
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int err = ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(
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resp->pke_resp_hdr.comn_resp_flags);
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char *ptr = areq->dst;
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err = (err == ICP_QAT_FW_COMN_STATUS_FLAG_OK) ? 0 : -EINVAL;
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if (req->src_align)
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dma_free_coherent(dev, req->ctx->key_sz, req->src_align,
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req->in.enc.m);
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else
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dma_unmap_single(dev, req->in.enc.m, req->ctx->key_sz,
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DMA_TO_DEVICE);
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dma_unmap_single(dev, req->out.enc.c, req->ctx->key_sz,
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DMA_FROM_DEVICE);
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dma_unmap_single(dev, req->phy_in, sizeof(struct qat_rsa_input_params),
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DMA_TO_DEVICE);
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dma_unmap_single(dev, req->phy_out,
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sizeof(struct qat_rsa_output_params),
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DMA_TO_DEVICE);
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areq->dst_len = req->ctx->key_sz;
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/* Need to set the corect length of the output */
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while (!(*ptr) && areq->dst_len) {
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areq->dst_len--;
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ptr++;
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}
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if (areq->dst_len != req->ctx->key_sz)
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memcpy(areq->dst, ptr, areq->dst_len);
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akcipher_request_complete(areq, err);
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}
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void qat_alg_asym_callback(void *_resp)
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{
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struct icp_qat_fw_pke_resp *resp = _resp;
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qat_rsa_cb(resp);
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}
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#define PKE_RSA_EP_512 0x1c161b21
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#define PKE_RSA_EP_1024 0x35111bf7
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#define PKE_RSA_EP_1536 0x4d111cdc
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#define PKE_RSA_EP_2048 0x6e111dba
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#define PKE_RSA_EP_3072 0x7d111ea3
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#define PKE_RSA_EP_4096 0xa5101f7e
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static unsigned long qat_rsa_enc_fn_id(unsigned int len)
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{
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unsigned int bitslen = len << 3;
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switch (bitslen) {
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case 512:
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return PKE_RSA_EP_512;
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case 1024:
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return PKE_RSA_EP_1024;
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case 1536:
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return PKE_RSA_EP_1536;
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case 2048:
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return PKE_RSA_EP_2048;
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case 3072:
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return PKE_RSA_EP_3072;
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case 4096:
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return PKE_RSA_EP_4096;
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default:
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return 0;
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};
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}
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#define PKE_RSA_DP1_512 0x1c161b3c
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#define PKE_RSA_DP1_1024 0x35111c12
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#define PKE_RSA_DP1_1536 0x4d111cf7
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#define PKE_RSA_DP1_2048 0x6e111dda
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#define PKE_RSA_DP1_3072 0x7d111ebe
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#define PKE_RSA_DP1_4096 0xa5101f98
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static unsigned long qat_rsa_dec_fn_id(unsigned int len)
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{
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unsigned int bitslen = len << 3;
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switch (bitslen) {
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case 512:
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return PKE_RSA_DP1_512;
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case 1024:
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return PKE_RSA_DP1_1024;
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case 1536:
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return PKE_RSA_DP1_1536;
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case 2048:
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return PKE_RSA_DP1_2048;
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case 3072:
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return PKE_RSA_DP1_3072;
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case 4096:
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return PKE_RSA_DP1_4096;
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default:
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return 0;
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};
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}
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static int qat_rsa_enc(struct akcipher_request *req)
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{
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struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
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struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
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struct qat_crypto_instance *inst = ctx->inst;
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struct device *dev = &GET_DEV(inst->accel_dev);
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struct qat_rsa_request *qat_req =
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PTR_ALIGN(akcipher_request_ctx(req), 64);
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struct icp_qat_fw_pke_request *msg = &qat_req->req;
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int ret, ctr = 0;
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if (unlikely(!ctx->n || !ctx->e))
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return -EINVAL;
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if (req->dst_len < ctx->key_sz) {
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req->dst_len = ctx->key_sz;
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return -EOVERFLOW;
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}
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memset(msg, '\0', sizeof(*msg));
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ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(msg->pke_hdr,
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ICP_QAT_FW_COMN_REQ_FLAG_SET);
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msg->pke_hdr.cd_pars.func_id = qat_rsa_enc_fn_id(ctx->key_sz);
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if (unlikely(!msg->pke_hdr.cd_pars.func_id))
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return -EINVAL;
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qat_req->ctx = ctx;
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msg->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
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msg->pke_hdr.comn_req_flags =
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ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_PTR_TYPE_FLAT,
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QAT_COMN_CD_FLD_TYPE_64BIT_ADR);
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qat_req->in.enc.e = ctx->dma_e;
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qat_req->in.enc.n = ctx->dma_n;
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ret = -ENOMEM;
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/*
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* src can be of any size in valid range, but HW expects it to be the
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* same as modulo n so in case it is different we need to allocate a
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* new buf and copy src data.
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* In other case we just need to map the user provided buffer.
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*/
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if (req->src_len < ctx->key_sz) {
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int shift = ctx->key_sz - req->src_len;
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qat_req->src_align = dma_zalloc_coherent(dev, ctx->key_sz,
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&qat_req->in.enc.m,
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GFP_KERNEL);
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if (unlikely(!qat_req->src_align))
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return ret;
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memcpy(qat_req->src_align + shift, req->src, req->src_len);
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} else {
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qat_req->src_align = NULL;
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qat_req->in.enc.m = dma_map_single(dev, req->src, req->src_len,
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DMA_TO_DEVICE);
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}
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qat_req->in.in_tab[3] = 0;
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qat_req->out.enc.c = dma_map_single(dev, req->dst, req->dst_len,
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DMA_FROM_DEVICE);
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qat_req->out.out_tab[1] = 0;
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qat_req->phy_in = dma_map_single(dev, &qat_req->in.enc.m,
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sizeof(struct qat_rsa_input_params),
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DMA_TO_DEVICE);
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qat_req->phy_out = dma_map_single(dev, &qat_req->out.enc.c,
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sizeof(struct qat_rsa_output_params),
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DMA_TO_DEVICE);
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if (unlikely((!qat_req->src_align &&
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dma_mapping_error(dev, qat_req->in.enc.m)) ||
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dma_mapping_error(dev, qat_req->out.enc.c) ||
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dma_mapping_error(dev, qat_req->phy_in) ||
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dma_mapping_error(dev, qat_req->phy_out)))
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goto unmap;
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msg->pke_mid.src_data_addr = qat_req->phy_in;
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msg->pke_mid.dest_data_addr = qat_req->phy_out;
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msg->pke_mid.opaque = (uint64_t)(__force long)req;
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msg->input_param_count = 3;
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msg->output_param_count = 1;
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do {
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ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg);
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} while (ret == -EBUSY && ctr++ < 100);
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if (!ret)
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return -EINPROGRESS;
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unmap:
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if (qat_req->src_align)
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dma_free_coherent(dev, ctx->key_sz, qat_req->src_align,
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qat_req->in.enc.m);
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else
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if (!dma_mapping_error(dev, qat_req->in.enc.m))
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dma_unmap_single(dev, qat_req->in.enc.m, ctx->key_sz,
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DMA_TO_DEVICE);
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if (!dma_mapping_error(dev, qat_req->out.enc.c))
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dma_unmap_single(dev, qat_req->out.enc.c, ctx->key_sz,
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DMA_FROM_DEVICE);
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if (!dma_mapping_error(dev, qat_req->phy_in))
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dma_unmap_single(dev, qat_req->phy_in,
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sizeof(struct qat_rsa_input_params),
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DMA_TO_DEVICE);
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if (!dma_mapping_error(dev, qat_req->phy_out))
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dma_unmap_single(dev, qat_req->phy_out,
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sizeof(struct qat_rsa_output_params),
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DMA_TO_DEVICE);
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return ret;
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}
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static int qat_rsa_dec(struct akcipher_request *req)
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{
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struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
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struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
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struct qat_crypto_instance *inst = ctx->inst;
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struct device *dev = &GET_DEV(inst->accel_dev);
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struct qat_rsa_request *qat_req =
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PTR_ALIGN(akcipher_request_ctx(req), 64);
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struct icp_qat_fw_pke_request *msg = &qat_req->req;
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int ret, ctr = 0;
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if (unlikely(!ctx->n || !ctx->d))
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return -EINVAL;
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if (req->dst_len < ctx->key_sz) {
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req->dst_len = ctx->key_sz;
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return -EOVERFLOW;
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}
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memset(msg, '\0', sizeof(*msg));
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ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(msg->pke_hdr,
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ICP_QAT_FW_COMN_REQ_FLAG_SET);
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msg->pke_hdr.cd_pars.func_id = qat_rsa_dec_fn_id(ctx->key_sz);
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if (unlikely(!msg->pke_hdr.cd_pars.func_id))
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return -EINVAL;
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qat_req->ctx = ctx;
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msg->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
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msg->pke_hdr.comn_req_flags =
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ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_PTR_TYPE_FLAT,
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QAT_COMN_CD_FLD_TYPE_64BIT_ADR);
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qat_req->in.dec.d = ctx->dma_d;
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qat_req->in.dec.n = ctx->dma_n;
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ret = -ENOMEM;
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/*
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* src can be of any size in valid range, but HW expects it to be the
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* same as modulo n so in case it is different we need to allocate a
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* new buf and copy src data.
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* In other case we just need to map the user provided buffer.
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*/
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if (req->src_len < ctx->key_sz) {
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int shift = ctx->key_sz - req->src_len;
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qat_req->src_align = dma_zalloc_coherent(dev, ctx->key_sz,
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&qat_req->in.dec.c,
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GFP_KERNEL);
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if (unlikely(!qat_req->src_align))
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return ret;
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memcpy(qat_req->src_align + shift, req->src, req->src_len);
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} else {
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qat_req->src_align = NULL;
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qat_req->in.dec.c = dma_map_single(dev, req->src, req->src_len,
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DMA_TO_DEVICE);
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}
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qat_req->in.in_tab[3] = 0;
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qat_req->out.dec.m = dma_map_single(dev, req->dst, req->dst_len,
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DMA_FROM_DEVICE);
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qat_req->out.out_tab[1] = 0;
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qat_req->phy_in = dma_map_single(dev, &qat_req->in.dec.c,
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sizeof(struct qat_rsa_input_params),
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DMA_TO_DEVICE);
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qat_req->phy_out = dma_map_single(dev, &qat_req->out.dec.m,
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sizeof(struct qat_rsa_output_params),
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DMA_TO_DEVICE);
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if (unlikely((!qat_req->src_align &&
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dma_mapping_error(dev, qat_req->in.dec.c)) ||
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dma_mapping_error(dev, qat_req->out.dec.m) ||
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dma_mapping_error(dev, qat_req->phy_in) ||
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dma_mapping_error(dev, qat_req->phy_out)))
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goto unmap;
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msg->pke_mid.src_data_addr = qat_req->phy_in;
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msg->pke_mid.dest_data_addr = qat_req->phy_out;
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msg->pke_mid.opaque = (uint64_t)(__force long)req;
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msg->input_param_count = 3;
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msg->output_param_count = 1;
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do {
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ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg);
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} while (ret == -EBUSY && ctr++ < 100);
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if (!ret)
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return -EINPROGRESS;
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unmap:
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if (qat_req->src_align)
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dma_free_coherent(dev, ctx->key_sz, qat_req->src_align,
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qat_req->in.dec.c);
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else
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if (!dma_mapping_error(dev, qat_req->in.dec.c))
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dma_unmap_single(dev, qat_req->in.dec.c, ctx->key_sz,
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DMA_TO_DEVICE);
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if (!dma_mapping_error(dev, qat_req->out.dec.m))
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dma_unmap_single(dev, qat_req->out.dec.m, ctx->key_sz,
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DMA_FROM_DEVICE);
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if (!dma_mapping_error(dev, qat_req->phy_in))
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dma_unmap_single(dev, qat_req->phy_in,
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sizeof(struct qat_rsa_input_params),
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DMA_TO_DEVICE);
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if (!dma_mapping_error(dev, qat_req->phy_out))
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dma_unmap_single(dev, qat_req->phy_out,
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sizeof(struct qat_rsa_output_params),
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DMA_TO_DEVICE);
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return ret;
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}
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int qat_rsa_get_n(void *context, size_t hdrlen, unsigned char tag,
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const void *value, size_t vlen)
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{
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struct qat_rsa_ctx *ctx = context;
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struct qat_crypto_instance *inst = ctx->inst;
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struct device *dev = &GET_DEV(inst->accel_dev);
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const char *ptr = value;
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int ret;
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while (!*ptr && vlen) {
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ptr++;
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vlen--;
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}
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|
|
|
ctx->key_sz = vlen;
|
|
ret = -EINVAL;
|
|
/* In FIPS mode only allow key size 2K & 3K */
|
|
if (fips_enabled && (ctx->key_sz != 256 && ctx->key_sz != 384)) {
|
|
pr_err("QAT: RSA: key size not allowed in FIPS mode\n");
|
|
goto err;
|
|
}
|
|
/* invalid key size provided */
|
|
if (!qat_rsa_enc_fn_id(ctx->key_sz))
|
|
goto err;
|
|
|
|
ret = -ENOMEM;
|
|
ctx->n = dma_zalloc_coherent(dev, ctx->key_sz, &ctx->dma_n, GFP_KERNEL);
|
|
if (!ctx->n)
|
|
goto err;
|
|
|
|
memcpy(ctx->n, ptr, ctx->key_sz);
|
|
return 0;
|
|
err:
|
|
ctx->key_sz = 0;
|
|
ctx->n = NULL;
|
|
return ret;
|
|
}
|
|
|
|
int qat_rsa_get_e(void *context, size_t hdrlen, unsigned char tag,
|
|
const void *value, size_t vlen)
|
|
{
|
|
struct qat_rsa_ctx *ctx = context;
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
|
const char *ptr = value;
|
|
|
|
while (!*ptr && vlen) {
|
|
ptr++;
|
|
vlen--;
|
|
}
|
|
|
|
if (!ctx->key_sz || !vlen || vlen > ctx->key_sz) {
|
|
ctx->e = NULL;
|
|
return -EINVAL;
|
|
}
|
|
|
|
ctx->e = dma_zalloc_coherent(dev, ctx->key_sz, &ctx->dma_e, GFP_KERNEL);
|
|
if (!ctx->e) {
|
|
ctx->e = NULL;
|
|
return -ENOMEM;
|
|
}
|
|
memcpy(ctx->e + (ctx->key_sz - vlen), ptr, vlen);
|
|
return 0;
|
|
}
|
|
|
|
int qat_rsa_get_d(void *context, size_t hdrlen, unsigned char tag,
|
|
const void *value, size_t vlen)
|
|
{
|
|
struct qat_rsa_ctx *ctx = context;
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
|
const char *ptr = value;
|
|
int ret;
|
|
|
|
while (!*ptr && vlen) {
|
|
ptr++;
|
|
vlen--;
|
|
}
|
|
|
|
ret = -EINVAL;
|
|
if (!ctx->key_sz || !vlen || vlen > ctx->key_sz)
|
|
goto err;
|
|
|
|
/* In FIPS mode only allow key size 2K & 3K */
|
|
if (fips_enabled && (vlen != 256 && vlen != 384)) {
|
|
pr_err("QAT: RSA: key size not allowed in FIPS mode\n");
|
|
goto err;
|
|
}
|
|
|
|
ret = -ENOMEM;
|
|
ctx->d = dma_zalloc_coherent(dev, ctx->key_sz, &ctx->dma_d, GFP_KERNEL);
|
|
if (!ctx->n)
|
|
goto err;
|
|
|
|
memcpy(ctx->d + (ctx->key_sz - vlen), ptr, vlen);
|
|
return 0;
|
|
err:
|
|
ctx->d = NULL;
|
|
return ret;
|
|
}
|
|
|
|
static int qat_rsa_setkey(struct crypto_akcipher *tfm, const void *key,
|
|
unsigned int keylen)
|
|
{
|
|
struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
|
|
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
|
|
int ret;
|
|
|
|
/* Free the old key if any */
|
|
if (ctx->n)
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->n, ctx->dma_n);
|
|
if (ctx->e)
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->e, ctx->dma_e);
|
|
if (ctx->d) {
|
|
memset(ctx->d, '\0', ctx->key_sz);
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->d, ctx->dma_d);
|
|
}
|
|
|
|
ctx->n = NULL;
|
|
ctx->e = NULL;
|
|
ctx->d = NULL;
|
|
ret = asn1_ber_decoder(&qat_rsakey_decoder, ctx, key, keylen);
|
|
if (ret < 0)
|
|
goto free;
|
|
|
|
if (!ctx->n || !ctx->e) {
|
|
/* invalid key provided */
|
|
ret = -EINVAL;
|
|
goto free;
|
|
}
|
|
|
|
return 0;
|
|
free:
|
|
if (ctx->d) {
|
|
memset(ctx->d, '\0', ctx->key_sz);
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->d, ctx->dma_d);
|
|
ctx->d = NULL;
|
|
}
|
|
if (ctx->e) {
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->e, ctx->dma_e);
|
|
ctx->e = NULL;
|
|
}
|
|
if (ctx->n) {
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->n, ctx->dma_n);
|
|
ctx->n = NULL;
|
|
ctx->key_sz = 0;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int qat_rsa_init_tfm(struct crypto_akcipher *tfm)
|
|
{
|
|
struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
|
|
struct qat_crypto_instance *inst =
|
|
qat_crypto_get_instance_node(get_current_node());
|
|
|
|
if (!inst)
|
|
return -EINVAL;
|
|
|
|
ctx->key_sz = 0;
|
|
ctx->inst = inst;
|
|
return 0;
|
|
}
|
|
|
|
static void qat_rsa_exit_tfm(struct crypto_akcipher *tfm)
|
|
{
|
|
struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
|
|
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
|
|
|
|
if (ctx->n)
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->n, ctx->dma_n);
|
|
if (ctx->e)
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->e, ctx->dma_e);
|
|
if (ctx->d) {
|
|
memset(ctx->d, '\0', ctx->key_sz);
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->d, ctx->dma_d);
|
|
}
|
|
qat_crypto_put_instance(ctx->inst);
|
|
ctx->n = NULL;
|
|
ctx->d = NULL;
|
|
ctx->d = NULL;
|
|
}
|
|
|
|
static struct akcipher_alg rsa = {
|
|
.encrypt = qat_rsa_enc,
|
|
.decrypt = qat_rsa_dec,
|
|
.sign = qat_rsa_dec,
|
|
.verify = qat_rsa_enc,
|
|
.setkey = qat_rsa_setkey,
|
|
.init = qat_rsa_init_tfm,
|
|
.exit = qat_rsa_exit_tfm,
|
|
.reqsize = sizeof(struct qat_rsa_request) + 64,
|
|
.base = {
|
|
.cra_name = "rsa",
|
|
.cra_driver_name = "qat-rsa",
|
|
.cra_priority = 1000,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_ctxsize = sizeof(struct qat_rsa_ctx),
|
|
},
|
|
};
|
|
|
|
int qat_asym_algs_register(void)
|
|
{
|
|
rsa.base.cra_flags = 0;
|
|
return crypto_register_akcipher(&rsa);
|
|
}
|
|
|
|
void qat_asym_algs_unregister(void)
|
|
{
|
|
crypto_unregister_akcipher(&rsa);
|
|
}
|