forked from Minki/linux
e8a64b20eb
The wrong define was used to check if the hqd is still active v2: Don't use SHIFT as the MASK is already shifted Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
671 lines
19 KiB
C
671 lines
19 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/fdtable.h>
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#include <linux/uaccess.h>
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_amdkfd.h"
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#include "cikd.h"
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#include "cik_sdma.h"
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#include "amdgpu_ucode.h"
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#include "gca/gfx_7_2_d.h"
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#include "gca/gfx_7_2_enum.h"
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#include "gca/gfx_7_2_sh_mask.h"
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#include "oss/oss_2_0_d.h"
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#include "oss/oss_2_0_sh_mask.h"
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#include "gmc/gmc_7_1_d.h"
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#include "gmc/gmc_7_1_sh_mask.h"
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#include "cik_structs.h"
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#define CIK_PIPE_PER_MEC (4)
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enum {
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MAX_TRAPID = 8, /* 3 bits in the bitfield. */
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MAX_WATCH_ADDRESSES = 4
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};
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enum {
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ADDRESS_WATCH_REG_ADDR_HI = 0,
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ADDRESS_WATCH_REG_ADDR_LO,
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ADDRESS_WATCH_REG_CNTL,
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ADDRESS_WATCH_REG_MAX
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};
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/* not defined in the CI/KV reg file */
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enum {
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ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
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ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
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ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
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/* extend the mask to 26 bits to match the low address field */
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ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
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ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
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};
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static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
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mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,
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mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,
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mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,
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mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
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};
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union TCP_WATCH_CNTL_BITS {
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struct {
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uint32_t mask:24;
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uint32_t vmid:4;
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uint32_t atc:1;
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uint32_t mode:2;
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uint32_t valid:1;
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} bitfields, bits;
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uint32_t u32All;
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signed int i32All;
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float f32All;
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};
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/*
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* Register access functions
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*/
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static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
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uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
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uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
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static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
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unsigned int vmid);
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static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t hpd_size, uint64_t hpd_gpu_addr);
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static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
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static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr);
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static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
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static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
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uint32_t pipe_id, uint32_t queue_id);
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static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
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unsigned int timeout, uint32_t pipe_id,
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uint32_t queue_id);
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static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
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static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
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unsigned int timeout);
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static int kgd_address_watch_disable(struct kgd_dev *kgd);
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static int kgd_address_watch_execute(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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uint32_t cntl_val,
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uint32_t addr_hi,
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uint32_t addr_lo);
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static int kgd_wave_control_execute(struct kgd_dev *kgd,
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uint32_t gfx_index_val,
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uint32_t sq_cmd);
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static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
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unsigned int watch_point_id,
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unsigned int reg_offset);
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static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
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static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
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uint8_t vmid);
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static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
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static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
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static const struct kfd2kgd_calls kfd2kgd = {
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.init_gtt_mem_allocation = alloc_gtt_mem,
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.free_gtt_mem = free_gtt_mem,
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.get_vmem_size = get_vmem_size,
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.get_gpu_clock_counter = get_gpu_clock_counter,
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.get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
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.program_sh_mem_settings = kgd_program_sh_mem_settings,
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.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
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.init_pipeline = kgd_init_pipeline,
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.init_interrupts = kgd_init_interrupts,
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.hqd_load = kgd_hqd_load,
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.hqd_sdma_load = kgd_hqd_sdma_load,
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.hqd_is_occupied = kgd_hqd_is_occupied,
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.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
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.hqd_destroy = kgd_hqd_destroy,
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.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
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.address_watch_disable = kgd_address_watch_disable,
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.address_watch_execute = kgd_address_watch_execute,
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.wave_control_execute = kgd_wave_control_execute,
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.address_watch_get_offset = kgd_address_watch_get_offset,
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.get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
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.get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
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.write_vmid_invalidate_request = write_vmid_invalidate_request,
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.get_fw_version = get_fw_version
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};
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struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions()
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{
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return (struct kfd2kgd_calls *)&kfd2kgd;
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}
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static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
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{
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return (struct amdgpu_device *)kgd;
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}
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static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
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uint32_t queue, uint32_t vmid)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
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mutex_lock(&adev->srbm_mutex);
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WREG32(mmSRBM_GFX_CNTL, value);
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}
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static void unlock_srbm(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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WREG32(mmSRBM_GFX_CNTL, 0);
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mutex_unlock(&adev->srbm_mutex);
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}
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static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t queue_id)
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{
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uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
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uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
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lock_srbm(kgd, mec, pipe, queue_id, 0);
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}
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static void release_queue(struct kgd_dev *kgd)
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{
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unlock_srbm(kgd);
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}
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static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
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uint32_t sh_mem_config,
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uint32_t sh_mem_ape1_base,
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uint32_t sh_mem_ape1_limit,
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uint32_t sh_mem_bases)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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lock_srbm(kgd, 0, 0, 0, vmid);
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WREG32(mmSH_MEM_CONFIG, sh_mem_config);
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WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
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WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
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WREG32(mmSH_MEM_BASES, sh_mem_bases);
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unlock_srbm(kgd);
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}
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static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
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unsigned int vmid)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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/*
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* We have to assume that there is no outstanding mapping.
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* The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
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* a mapping is in progress or because a mapping finished and the
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* SW cleared it. So the protocol is to always wait & clear.
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*/
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uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
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ATC_VMID0_PASID_MAPPING__VALID_MASK;
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WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
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while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
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cpu_relax();
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WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
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/* Mapping vmid to pasid also for IH block */
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WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
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return 0;
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}
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static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
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uint32_t hpd_size, uint64_t hpd_gpu_addr)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
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uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
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lock_srbm(kgd, mec, pipe, 0, 0);
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WREG32(mmCP_HPD_EOP_BASE_ADDR, lower_32_bits(hpd_gpu_addr >> 8));
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WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(hpd_gpu_addr >> 8));
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WREG32(mmCP_HPD_EOP_VMID, 0);
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WREG32(mmCP_HPD_EOP_CONTROL, hpd_size);
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unlock_srbm(kgd);
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return 0;
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}
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static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t mec;
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uint32_t pipe;
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mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
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pipe = (pipe_id % CIK_PIPE_PER_MEC);
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lock_srbm(kgd, mec, pipe, 0, 0);
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WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
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CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
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unlock_srbm(kgd);
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return 0;
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}
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static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
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{
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uint32_t retval;
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retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
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m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
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pr_debug("kfd: sdma base address: 0x%x\n", retval);
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return retval;
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}
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static inline struct cik_mqd *get_mqd(void *mqd)
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{
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return (struct cik_mqd *)mqd;
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}
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static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
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{
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return (struct cik_sdma_rlc_registers *)mqd;
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}
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static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
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uint32_t queue_id, uint32_t __user *wptr)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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uint32_t wptr_shadow, is_wptr_shadow_valid;
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struct cik_mqd *m;
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m = get_mqd(mqd);
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is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
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acquire_queue(kgd, pipe_id, queue_id);
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WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
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WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
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WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control);
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WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
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WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
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WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
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WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
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WREG32(mmCP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
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WREG32(mmCP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
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WREG32(mmCP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
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WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state);
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WREG32(mmCP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
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WREG32(mmCP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
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WREG32(mmCP_HQD_ATOMIC0_PREOP_LO, m->cp_hqd_atomic0_preop_lo);
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WREG32(mmCP_HQD_ATOMIC0_PREOP_HI, m->cp_hqd_atomic0_preop_hi);
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WREG32(mmCP_HQD_ATOMIC1_PREOP_LO, m->cp_hqd_atomic1_preop_lo);
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WREG32(mmCP_HQD_ATOMIC1_PREOP_HI, m->cp_hqd_atomic1_preop_hi);
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WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo);
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WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
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m->cp_hqd_pq_rptr_report_addr_hi);
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WREG32(mmCP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
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WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, m->cp_hqd_pq_wptr_poll_addr_lo);
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WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, m->cp_hqd_pq_wptr_poll_addr_hi);
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WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control);
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WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid);
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WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum);
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WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
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WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
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WREG32(mmCP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
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if (is_wptr_shadow_valid)
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WREG32(mmCP_HQD_PQ_WPTR, wptr_shadow);
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WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active);
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release_queue(kgd);
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return 0;
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}
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static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
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{
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struct amdgpu_device *adev = get_amdgpu_device(kgd);
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struct cik_sdma_rlc_registers *m;
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uint32_t sdma_base_addr;
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m = get_sdma_mqd(mqd);
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sdma_base_addr = get_sdma_base_addr(m);
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WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
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m->sdma_rlc_virtual_addr);
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WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE,
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m->sdma_rlc_rb_base);
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WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
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m->sdma_rlc_rb_base_hi);
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WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
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m->sdma_rlc_rb_rptr_addr_lo);
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WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
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m->sdma_rlc_rb_rptr_addr_hi);
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WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
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m->sdma_rlc_doorbell);
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WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
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m->sdma_rlc_rb_cntl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
|
|
uint32_t pipe_id, uint32_t queue_id)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
uint32_t act;
|
|
bool retval = false;
|
|
uint32_t low, high;
|
|
|
|
acquire_queue(kgd, pipe_id, queue_id);
|
|
act = RREG32(mmCP_HQD_ACTIVE);
|
|
if (act) {
|
|
low = lower_32_bits(queue_address >> 8);
|
|
high = upper_32_bits(queue_address >> 8);
|
|
|
|
if (low == RREG32(mmCP_HQD_PQ_BASE) &&
|
|
high == RREG32(mmCP_HQD_PQ_BASE_HI))
|
|
retval = true;
|
|
}
|
|
release_queue(kgd);
|
|
return retval;
|
|
}
|
|
|
|
static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
struct cik_sdma_rlc_registers *m;
|
|
uint32_t sdma_base_addr;
|
|
uint32_t sdma_rlc_rb_cntl;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_base_addr = get_sdma_base_addr(m);
|
|
|
|
sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
|
|
|
|
if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
|
|
unsigned int timeout, uint32_t pipe_id,
|
|
uint32_t queue_id)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
uint32_t temp;
|
|
|
|
acquire_queue(kgd, pipe_id, queue_id);
|
|
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
|
|
|
|
WREG32(mmCP_HQD_DEQUEUE_REQUEST, reset_type);
|
|
|
|
while (true) {
|
|
temp = RREG32(mmCP_HQD_ACTIVE);
|
|
if (temp & CP_HQD_ACTIVE__ACTIVE_MASK)
|
|
break;
|
|
if (timeout == 0) {
|
|
pr_err("kfd: cp queue preemption time out (%dms)\n",
|
|
temp);
|
|
release_queue(kgd);
|
|
return -ETIME;
|
|
}
|
|
msleep(20);
|
|
timeout -= 20;
|
|
}
|
|
|
|
release_queue(kgd);
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
|
|
unsigned int timeout)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
struct cik_sdma_rlc_registers *m;
|
|
uint32_t sdma_base_addr;
|
|
uint32_t temp;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_base_addr = get_sdma_base_addr(m);
|
|
|
|
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
|
|
temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
|
|
|
|
while (true) {
|
|
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
|
|
if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
|
|
break;
|
|
if (timeout == 0)
|
|
return -ETIME;
|
|
msleep(20);
|
|
timeout -= 20;
|
|
}
|
|
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
|
|
WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_address_watch_disable(struct kgd_dev *kgd)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
union TCP_WATCH_CNTL_BITS cntl;
|
|
unsigned int i;
|
|
|
|
cntl.u32All = 0;
|
|
|
|
cntl.bitfields.valid = 0;
|
|
cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
|
|
cntl.bitfields.atc = 1;
|
|
|
|
/* Turning off this address until we set all the registers */
|
|
for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
|
|
WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_CNTL], cntl.u32All);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_address_watch_execute(struct kgd_dev *kgd,
|
|
unsigned int watch_point_id,
|
|
uint32_t cntl_val,
|
|
uint32_t addr_hi,
|
|
uint32_t addr_lo)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
union TCP_WATCH_CNTL_BITS cntl;
|
|
|
|
cntl.u32All = cntl_val;
|
|
|
|
/* Turning off this watch point until we set all the registers */
|
|
cntl.bitfields.valid = 0;
|
|
WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_CNTL], cntl.u32All);
|
|
|
|
WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_ADDR_HI], addr_hi);
|
|
|
|
WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_ADDR_LO], addr_lo);
|
|
|
|
/* Enable the watch point */
|
|
cntl.bitfields.valid = 1;
|
|
|
|
WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
|
|
ADDRESS_WATCH_REG_CNTL], cntl.u32All);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_wave_control_execute(struct kgd_dev *kgd,
|
|
uint32_t gfx_index_val,
|
|
uint32_t sq_cmd)
|
|
{
|
|
struct amdgpu_device *adev = get_amdgpu_device(kgd);
|
|
uint32_t data;
|
|
|
|
mutex_lock(&adev->grbm_idx_mutex);
|
|
|
|
WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
|
|
WREG32(mmSQ_CMD, sq_cmd);
|
|
|
|
/* Restore the GRBM_GFX_INDEX register */
|
|
|
|
data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK |
|
|
GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
|
|
GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
|
|
|
|
WREG32(mmGRBM_GFX_INDEX, data);
|
|
|
|
mutex_unlock(&adev->grbm_idx_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
|
|
unsigned int watch_point_id,
|
|
unsigned int reg_offset)
|
|
{
|
|
return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
|
|
}
|
|
|
|
static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
|
|
uint8_t vmid)
|
|
{
|
|
uint32_t reg;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
|
|
reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
|
|
return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
|
|
}
|
|
|
|
static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
|
|
uint8_t vmid)
|
|
{
|
|
uint32_t reg;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
|
|
reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
|
|
return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
|
|
}
|
|
|
|
static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
|
|
WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
|
|
}
|
|
|
|
static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
|
|
const union amdgpu_firmware_header *hdr;
|
|
|
|
BUG_ON(kgd == NULL);
|
|
|
|
switch (type) {
|
|
case KGD_ENGINE_PFP:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.pfp_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_ME:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.me_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_CE:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.ce_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_MEC1:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.mec_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_MEC2:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.mec2_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_RLC:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->gfx.rlc_fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_SDMA1:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->sdma[0].fw->data;
|
|
break;
|
|
|
|
case KGD_ENGINE_SDMA2:
|
|
hdr = (const union amdgpu_firmware_header *)
|
|
adev->sdma[1].fw->data;
|
|
break;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
if (hdr == NULL)
|
|
return 0;
|
|
|
|
/* Only 12 bit in use*/
|
|
return hdr->common.ucode_version;
|
|
}
|
|
|