forked from Minki/linux
3c7b536232
sh-hspi driver which doesn't need platform data at the time of registration can be registerd on SoC. And, registering these drivers in the SoC code can avoid unwanted device numbering issue. (ex. the hspi2 device number will be spi.0 if hspi2 only registered) This patch registers it on SoC code as cleanup C code Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
415 lines
10 KiB
C
415 lines
10 KiB
C
/*
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* r8a7778 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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* Copyright (C) 2013 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <linux/platform_device.h>
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#include <linux/irqchip.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <linux/pm_runtime.h>
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#include <linux/usb/phy.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <linux/usb/ohci_pdriver.h>
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#include <linux/dma-mapping.h>
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#include <mach/irqs.h>
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#include <mach/r8a7778.h>
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#include <mach/common.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/cache-l2x0.h>
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/* SCIF */
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#define SCIF_INFO(baseaddr, irq) \
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{ \
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.mapbase = baseaddr, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
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.scbrr_algo_id = SCBRR_ALGO_2, \
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.type = PORT_SCIF, \
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.irqs = SCIx_IRQ_MUXED(irq), \
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}
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static struct plat_sci_port scif_platform_data[] __initdata = {
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SCIF_INFO(0xffe40000, gic_iid(0x66)),
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SCIF_INFO(0xffe41000, gic_iid(0x67)),
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SCIF_INFO(0xffe42000, gic_iid(0x68)),
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SCIF_INFO(0xffe43000, gic_iid(0x69)),
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SCIF_INFO(0xffe44000, gic_iid(0x6a)),
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SCIF_INFO(0xffe45000, gic_iid(0x6b)),
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};
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/* TMU */
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static struct resource sh_tmu0_resources[] __initdata = {
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DEFINE_RES_MEM(0xffd80008, 12),
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DEFINE_RES_IRQ(gic_iid(0x40)),
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};
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static struct sh_timer_config sh_tmu0_platform_data __initdata = {
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.name = "TMU00",
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.channel_offset = 0x4,
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.timer_bit = 0,
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.clockevent_rating = 200,
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};
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static struct resource sh_tmu1_resources[] __initdata = {
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DEFINE_RES_MEM(0xffd80014, 12),
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DEFINE_RES_IRQ(gic_iid(0x41)),
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};
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static struct sh_timer_config sh_tmu1_platform_data __initdata = {
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.name = "TMU01",
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clocksource_rating = 200,
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};
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#define r8a7778_register_tmu(idx) \
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platform_device_register_resndata( \
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&platform_bus, "sh_tmu", idx, \
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sh_tmu##idx##_resources, \
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ARRAY_SIZE(sh_tmu##idx##_resources), \
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&sh_tmu##idx##_platform_data, \
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sizeof(sh_tmu##idx##_platform_data))
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/* USB */
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static struct usb_phy *phy;
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static int usb_power_on(struct platform_device *pdev)
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{
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if (IS_ERR(phy))
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return PTR_ERR(phy);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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usb_phy_init(phy);
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return 0;
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}
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static void usb_power_off(struct platform_device *pdev)
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{
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if (IS_ERR(phy))
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return;
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usb_phy_shutdown(phy);
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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}
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static int ehci_init_internal_buffer(struct usb_hcd *hcd)
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{
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/*
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* Below are recommended values from the datasheet;
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* see [USB :: Setting of EHCI Internal Buffer].
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*/
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/* EHCI IP internal buffer setting */
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iowrite32(0x00ff0040, hcd->regs + 0x0094);
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/* EHCI IP internal buffer enable */
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iowrite32(0x00000001, hcd->regs + 0x009C);
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return 0;
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}
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static struct usb_ehci_pdata ehci_pdata __initdata = {
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.power_on = usb_power_on,
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.power_off = usb_power_off,
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.power_suspend = usb_power_off,
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.pre_setup = ehci_init_internal_buffer,
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};
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static struct resource ehci_resources[] __initdata = {
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DEFINE_RES_MEM(0xffe70000, 0x400),
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DEFINE_RES_IRQ(gic_iid(0x4c)),
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};
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static struct usb_ohci_pdata ohci_pdata __initdata = {
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.power_on = usb_power_on,
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.power_off = usb_power_off,
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.power_suspend = usb_power_off,
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};
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static struct resource ohci_resources[] __initdata = {
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DEFINE_RES_MEM(0xffe70400, 0x400),
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DEFINE_RES_IRQ(gic_iid(0x4c)),
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};
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#define USB_PLATFORM_INFO(hci) \
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static struct platform_device_info hci##_info __initdata = { \
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.parent = &platform_bus, \
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.name = #hci "-platform", \
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.id = -1, \
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.res = hci##_resources, \
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.num_res = ARRAY_SIZE(hci##_resources), \
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.data = &hci##_pdata, \
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.size_data = sizeof(hci##_pdata), \
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.dma_mask = DMA_BIT_MASK(32), \
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}
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USB_PLATFORM_INFO(ehci);
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USB_PLATFORM_INFO(ohci);
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/* Ether */
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static struct resource ether_resources[] __initdata = {
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DEFINE_RES_MEM(0xfde00000, 0x400),
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DEFINE_RES_IRQ(gic_iid(0x89)),
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};
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void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
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{
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platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
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ether_resources,
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ARRAY_SIZE(ether_resources),
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pdata, sizeof(*pdata));
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}
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/* PFC/GPIO */
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static struct resource pfc_resources[] __initdata = {
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DEFINE_RES_MEM(0xfffc0000, 0x118),
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};
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#define R8A7778_GPIO(idx) \
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static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \
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DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \
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DEFINE_RES_IRQ(gic_iid(0x87)), \
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}; \
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\
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static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
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.gpio_base = 32 * (idx), \
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.irq_base = GPIO_IRQ_BASE(idx), \
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.number_of_pins = 32, \
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.pctl_name = "pfc-r8a7778", \
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}
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R8A7778_GPIO(0);
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R8A7778_GPIO(1);
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R8A7778_GPIO(2);
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R8A7778_GPIO(3);
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R8A7778_GPIO(4);
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#define r8a7778_register_gpio(idx) \
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platform_device_register_resndata( \
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&platform_bus, "gpio_rcar", idx, \
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r8a7778_gpio##idx##_resources, \
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ARRAY_SIZE(r8a7778_gpio##idx##_resources), \
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&r8a7778_gpio##idx##_platform_data, \
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sizeof(r8a7778_gpio##idx##_platform_data))
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void __init r8a7778_pinmux_init(void)
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{
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platform_device_register_simple(
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"pfc-r8a7778", -1,
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pfc_resources,
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ARRAY_SIZE(pfc_resources));
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r8a7778_register_gpio(0);
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r8a7778_register_gpio(1);
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r8a7778_register_gpio(2);
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r8a7778_register_gpio(3);
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r8a7778_register_gpio(4);
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};
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/* I2C */
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static struct resource i2c_resources[] __initdata = {
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/* I2C0 */
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DEFINE_RES_MEM(0xffc70000, 0x1000),
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DEFINE_RES_IRQ(gic_iid(0x63)),
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/* I2C1 */
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DEFINE_RES_MEM(0xffc71000, 0x1000),
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DEFINE_RES_IRQ(gic_iid(0x6e)),
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/* I2C2 */
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DEFINE_RES_MEM(0xffc72000, 0x1000),
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DEFINE_RES_IRQ(gic_iid(0x6c)),
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/* I2C3 */
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DEFINE_RES_MEM(0xffc73000, 0x1000),
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DEFINE_RES_IRQ(gic_iid(0x6d)),
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};
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static void __init r8a7778_register_i2c(int id)
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{
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BUG_ON(id < 0 || id > 3);
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platform_device_register_simple(
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"i2c-rcar", id,
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i2c_resources + (2 * id), 2);
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}
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/* HSPI */
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static struct resource hspi_resources[] __initdata = {
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/* HSPI0 */
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DEFINE_RES_MEM(0xfffc7000, 0x18),
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DEFINE_RES_IRQ(gic_iid(0x5f)),
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/* HSPI1 */
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DEFINE_RES_MEM(0xfffc8000, 0x18),
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DEFINE_RES_IRQ(gic_iid(0x74)),
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/* HSPI2 */
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DEFINE_RES_MEM(0xfffc6000, 0x18),
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DEFINE_RES_IRQ(gic_iid(0x75)),
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};
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void __init r8a7778_register_hspi(int id)
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{
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BUG_ON(id < 0 || id > 2);
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platform_device_register_simple(
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"sh-hspi", id,
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hspi_resources + (2 * id), 2);
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}
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void __init r8a7778_add_dt_devices(void)
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{
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int i;
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
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if (base) {
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/*
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* Early BRESP enable, Shared attribute override enable, 64K*16way
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* don't call iounmap(base)
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*/
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l2x0_init(base, 0x40470000, 0x82000fff);
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}
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#endif
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for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
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platform_device_register_data(&platform_bus, "sh-sci", i,
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&scif_platform_data[i],
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sizeof(struct plat_sci_port));
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r8a7778_register_tmu(0);
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r8a7778_register_tmu(1);
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}
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void __init r8a7778_add_standard_devices(void)
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{
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r8a7778_add_dt_devices();
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r8a7778_register_i2c(0);
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r8a7778_register_i2c(1);
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r8a7778_register_i2c(2);
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r8a7778_register_i2c(3);
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r8a7778_register_hspi(0);
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r8a7778_register_hspi(1);
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r8a7778_register_hspi(2);
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}
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void __init r8a7778_init_late(void)
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{
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phy = usb_get_phy(USB_PHY_TYPE_USB2);
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platform_device_register_full(&ehci_info);
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platform_device_register_full(&ohci_info);
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}
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static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
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.sense_bitfield_width = 2,
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};
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static struct resource irqpin_resources[] __initdata = {
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DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
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DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
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DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
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DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
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DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
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DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
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};
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void __init r8a7778_init_irq_extpin(int irlm)
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{
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void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
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unsigned long tmp;
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if (!icr0) {
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pr_warn("r8a7778: unable to setup external irq pin mode\n");
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return;
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}
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tmp = ioread32(icr0);
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if (irlm)
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tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
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else
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tmp &= ~(1 << 23); /* IRL mode - not supported */
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tmp |= (1 << 21); /* LVLMODE = 1 */
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iowrite32(tmp, icr0);
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iounmap(icr0);
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if (irlm)
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platform_device_register_resndata(
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&platform_bus, "renesas_intc_irqpin", -1,
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irqpin_resources, ARRAY_SIZE(irqpin_resources),
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&irqpin_platform_data, sizeof(irqpin_platform_data));
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}
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void __init r8a7778_init_delay(void)
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{
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shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
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}
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#ifdef CONFIG_USE_OF
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#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
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#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
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#define INT2NTSR0 0x00018 /* 0xfe700018 */
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#define INT2NTSR1 0x0002c /* 0xfe70002c */
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void __init r8a7778_init_irq_dt(void)
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{
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void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
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BUG_ON(!base);
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irqchip_init();
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/* route all interrupts to ARM */
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__raw_writel(0x73ffffff, base + INT2NTSR0);
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__raw_writel(0xffffffff, base + INT2NTSR1);
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/* unmask all known interrupts in INTCS2 */
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__raw_writel(0x08330773, base + INT2SMSKCR0);
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__raw_writel(0x00311110, base + INT2SMSKCR1);
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iounmap(base);
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}
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static const char *r8a7778_compat_dt[] __initdata = {
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"renesas,r8a7778",
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NULL,
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};
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DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
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.init_early = r8a7778_init_delay,
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.init_irq = r8a7778_init_irq_dt,
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.init_time = shmobile_timer_init,
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.dt_compat = r8a7778_compat_dt,
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.init_late = r8a7778_init_late,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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