forked from Minki/linux
1190338f50
exynos_audss_clk_init() is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
134 lines
3.8 KiB
C
134 lines
3.8 KiB
C
/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Padmavathi Venna <padma.v@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for Audio Subsystem Clock Controller.
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*/
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/clk/exynos-audss-clk.h>
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static DEFINE_SPINLOCK(lock);
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static struct clk **clk_table;
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static void __iomem *reg_base;
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static struct clk_onecell_data clk_data;
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#define ASS_CLK_SRC 0x0
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#define ASS_CLK_DIV 0x4
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#define ASS_CLK_GATE 0x8
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static unsigned long reg_save[][2] = {
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{ASS_CLK_SRC, 0},
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{ASS_CLK_DIV, 0},
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{ASS_CLK_GATE, 0},
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};
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/* list of all parent clock list */
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static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
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static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
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#ifdef CONFIG_PM_SLEEP
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static int exynos_audss_clk_suspend(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(reg_save); i++)
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reg_save[i][1] = readl(reg_base + reg_save[i][0]);
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return 0;
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}
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static void exynos_audss_clk_resume(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(reg_save); i++)
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writel(reg_save[i][1], reg_base + reg_save[i][0]);
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}
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static struct syscore_ops exynos_audss_clk_syscore_ops = {
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.suspend = exynos_audss_clk_suspend,
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.resume = exynos_audss_clk_resume,
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};
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#endif /* CONFIG_PM_SLEEP */
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/* register exynos_audss clocks */
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static void __init exynos_audss_clk_init(struct device_node *np)
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{
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_err("%s: failed to map audss registers\n", __func__);
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return;
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}
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clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
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GFP_KERNEL);
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if (!clk_table) {
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pr_err("%s: could not allocate clk lookup table\n", __func__);
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return;
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}
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clk_data.clks = clk_table;
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clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
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mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
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reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
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clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
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mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
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reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
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clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
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"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
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0, &lock);
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clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
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"dout_aud_bus", "dout_srp", 0,
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reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
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clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
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"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
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&lock);
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clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
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"dout_srp", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 0, 0, &lock);
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clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
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"dout_aud_bus", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 2, 0, &lock);
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clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
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"dout_i2s", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 3, 0, &lock);
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clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
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"sclk_pcm", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 4, 0, &lock);
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clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
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"div_pcm0", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 5, 0, &lock);
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#ifdef CONFIG_PM_SLEEP
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register_syscore_ops(&exynos_audss_clk_syscore_ops);
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#endif
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pr_info("Exynos: Audss: clock setup completed\n");
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}
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CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
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exynos_audss_clk_init);
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CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
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exynos_audss_clk_init);
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