forked from Minki/linux
3c4da74fe5
Both the PAL and NTSC standards are interlaced where a
frame consist of two fields. Total number of lines in a frame in both systems
are an odd number so the two fields will have different length.
In the 625 line standard ("PAL") the odd field of the frame is transmitted first,
while in the 525 standard ("NTSC") the even field is transmitted first.
This adds the possibility to change output config between the fields and standards.
This setting will reduce the "format-jitter" on the signal sent by the pixelport
moving the difference between the fields to vertical front/back-porch only.
Signed-off-by: Martin Bugge <marbugge@cisco.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
229 lines
6.0 KiB
C
229 lines
6.0 KiB
C
/*
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* adv7842 - Analog Devices ADV7842 video decoder driver
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*
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* Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef _ADV7842_
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#define _ADV7842_
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/* Analog input muxing modes (AFE register 0x02, [2:0]) */
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enum adv7842_ain_sel {
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ADV7842_AIN1_2_3_NC_SYNC_1_2 = 0,
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ADV7842_AIN4_5_6_NC_SYNC_2_1 = 1,
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ADV7842_AIN7_8_9_NC_SYNC_3_1 = 2,
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ADV7842_AIN10_11_12_NC_SYNC_4_1 = 3,
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ADV7842_AIN9_4_5_6_SYNC_2_1 = 4,
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};
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/* Bus rotation and reordering (IO register 0x04, [7:5]) */
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enum adv7842_op_ch_sel {
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ADV7842_OP_CH_SEL_GBR = 0,
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ADV7842_OP_CH_SEL_GRB = 1,
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ADV7842_OP_CH_SEL_BGR = 2,
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ADV7842_OP_CH_SEL_RGB = 3,
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ADV7842_OP_CH_SEL_BRG = 4,
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ADV7842_OP_CH_SEL_RBG = 5,
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};
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/* Mode of operation */
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enum adv7842_mode {
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ADV7842_MODE_SDP,
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ADV7842_MODE_COMP,
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ADV7842_MODE_RGB,
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ADV7842_MODE_HDMI
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};
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/* Video standard select (IO register 0x00, [5:0]) */
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enum adv7842_vid_std_select {
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/* SDP */
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ADV7842_SDP_VID_STD_CVBS_SD_4x1 = 0x01,
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ADV7842_SDP_VID_STD_YC_SD4_x1 = 0x09,
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/* RGB */
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ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE = 0x07,
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/* HDMI GR */
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ADV7842_HDMI_GR_VID_STD_AUTO_GRAPH_MODE = 0x02,
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/* HDMI COMP */
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ADV7842_HDMI_COMP_VID_STD_HD_1250P = 0x1e,
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};
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/* Input Color Space (IO register 0x02, [7:4]) */
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enum adv7842_inp_color_space {
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ADV7842_INP_COLOR_SPACE_LIM_RGB = 0,
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ADV7842_INP_COLOR_SPACE_FULL_RGB = 1,
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ADV7842_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
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ADV7842_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
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ADV7842_INP_COLOR_SPACE_XVYCC_601 = 4,
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ADV7842_INP_COLOR_SPACE_XVYCC_709 = 5,
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ADV7842_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
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ADV7842_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
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ADV7842_INP_COLOR_SPACE_AUTO = 0xf,
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};
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/* Select output format (IO register 0x03, [7:0]) */
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enum adv7842_op_format_sel {
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ADV7842_OP_FORMAT_SEL_SDR_ITU656_8 = 0x00,
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ADV7842_OP_FORMAT_SEL_SDR_ITU656_10 = 0x01,
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ADV7842_OP_FORMAT_SEL_SDR_ITU656_12_MODE0 = 0x02,
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ADV7842_OP_FORMAT_SEL_SDR_ITU656_12_MODE1 = 0x06,
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ADV7842_OP_FORMAT_SEL_SDR_ITU656_12_MODE2 = 0x0a,
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ADV7842_OP_FORMAT_SEL_DDR_422_8 = 0x20,
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ADV7842_OP_FORMAT_SEL_DDR_422_10 = 0x21,
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ADV7842_OP_FORMAT_SEL_DDR_422_12_MODE0 = 0x22,
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ADV7842_OP_FORMAT_SEL_DDR_422_12_MODE1 = 0x23,
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ADV7842_OP_FORMAT_SEL_DDR_422_12_MODE2 = 0x24,
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ADV7842_OP_FORMAT_SEL_SDR_444_24 = 0x40,
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ADV7842_OP_FORMAT_SEL_SDR_444_30 = 0x41,
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ADV7842_OP_FORMAT_SEL_SDR_444_36_MODE0 = 0x42,
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ADV7842_OP_FORMAT_SEL_DDR_444_24 = 0x60,
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ADV7842_OP_FORMAT_SEL_DDR_444_30 = 0x61,
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ADV7842_OP_FORMAT_SEL_DDR_444_36 = 0x62,
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ADV7842_OP_FORMAT_SEL_SDR_ITU656_16 = 0x80,
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ADV7842_OP_FORMAT_SEL_SDR_ITU656_20 = 0x81,
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ADV7842_OP_FORMAT_SEL_SDR_ITU656_24_MODE0 = 0x82,
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ADV7842_OP_FORMAT_SEL_SDR_ITU656_24_MODE1 = 0x86,
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ADV7842_OP_FORMAT_SEL_SDR_ITU656_24_MODE2 = 0x8a,
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};
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enum adv7842_select_input {
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ADV7842_SELECT_HDMI_PORT_A,
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ADV7842_SELECT_HDMI_PORT_B,
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ADV7842_SELECT_VGA_RGB,
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ADV7842_SELECT_VGA_COMP,
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ADV7842_SELECT_SDP_CVBS,
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ADV7842_SELECT_SDP_YC,
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};
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struct adv7842_sdp_csc_coeff {
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bool manual;
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uint16_t scaling;
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uint16_t A1;
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uint16_t A2;
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uint16_t A3;
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uint16_t A4;
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uint16_t B1;
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uint16_t B2;
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uint16_t B3;
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uint16_t B4;
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uint16_t C1;
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uint16_t C2;
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uint16_t C3;
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uint16_t C4;
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};
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struct adv7842_sdp_io_sync_adjustment {
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bool adjust;
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uint16_t hs_beg;
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uint16_t hs_width;
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uint16_t de_beg;
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uint16_t de_end;
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uint8_t de_v_beg_o;
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uint8_t de_v_beg_e;
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uint8_t de_v_end_o;
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uint8_t de_v_end_e;
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};
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/* Platform dependent definition */
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struct adv7842_platform_data {
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/* connector - HDMI or DVI? */
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unsigned connector_hdmi:1;
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/* chip reset during probe */
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unsigned chip_reset:1;
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/* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
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unsigned disable_pwrdnb:1;
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/* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
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unsigned disable_cable_det_rst:1;
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/* Analog input muxing mode */
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enum adv7842_ain_sel ain_sel;
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/* Bus rotation and reordering */
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enum adv7842_op_ch_sel op_ch_sel;
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/* Default mode */
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enum adv7842_mode mode;
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/* Video standard */
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enum adv7842_vid_std_select vid_std_select;
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/* Select output format */
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enum adv7842_op_format_sel op_format_sel;
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/* IO register 0x02 */
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unsigned alt_gamma:1;
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unsigned op_656_range:1;
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unsigned rgb_out:1;
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unsigned alt_data_sat:1;
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/* IO register 0x05 */
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unsigned blank_data:1;
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unsigned insert_av_codes:1;
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unsigned replicate_av_codes:1;
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unsigned invert_cbcr:1;
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/* IO register 0x30 */
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unsigned output_bus_lsb_to_msb:1;
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/* IO register 0x14 */
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struct {
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unsigned data:2;
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unsigned clock:2;
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unsigned sync:2;
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} drive_strength;
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/* External RAM for 3-D comb or frame synchronizer */
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unsigned sd_ram_size; /* ram size in MB */
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unsigned sd_ram_ddr:1; /* ddr or sdr sdram */
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/* Free run */
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unsigned hdmi_free_run_mode;
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struct adv7842_sdp_csc_coeff sdp_csc_coeff;
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struct adv7842_sdp_io_sync_adjustment sdp_io_sync_625;
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struct adv7842_sdp_io_sync_adjustment sdp_io_sync_525;
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/* i2c addresses */
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u8 i2c_sdp_io;
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u8 i2c_sdp;
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u8 i2c_cp;
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u8 i2c_vdp;
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u8 i2c_afe;
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u8 i2c_hdmi;
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u8 i2c_repeater;
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u8 i2c_edid;
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u8 i2c_infoframe;
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u8 i2c_cec;
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u8 i2c_avlink;
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};
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#define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
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#define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
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#define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
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/* notify events */
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#define ADV7842_FMT_CHANGE 1
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/* custom ioctl, used to test the external RAM that's used by the
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* deinterlacer. */
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#define ADV7842_CMD_RAM_TEST _IO('V', BASE_VIDIOC_PRIVATE)
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#endif
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