forked from Minki/linux
b4d2394d01
This change makes it so that instead of passing and storing a mii_bus we instead pass and store a host_dev. From there we can test to determine the exact type of device, and can verify it is the correct device for our switch. So for example it would be possible to pass a device pointer from a pci_dev and instead of checking for a PHY ID we could check for a vendor and/or device ID. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
412 lines
11 KiB
C
412 lines
11 KiB
C
/* net/dsa/mv88e6171.c - Marvell 88e6171 switch chip support
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* Copyright (c) 2008-2009 Marvell Semiconductor
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* Copyright (c) 2014 Claudio Leite <leitec@staticky.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
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#include "mv88e6xxx.h"
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static char *mv88e6171_probe(struct device *host_dev, int sw_addr)
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{
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struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
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int ret;
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if (bus == NULL)
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return NULL;
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ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
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if (ret >= 0) {
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if ((ret & 0xfff0) == 0x1710)
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return "Marvell 88E6171";
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}
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return NULL;
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}
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static int mv88e6171_switch_reset(struct dsa_switch *ds)
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{
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int i;
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int ret;
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unsigned long timeout;
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/* Set all ports to the disabled state. */
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for (i = 0; i < 8; i++) {
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ret = REG_READ(REG_PORT(i), 0x04);
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REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
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}
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/* Wait for transmit queues to drain. */
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usleep_range(2000, 4000);
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/* Reset the switch. */
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REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
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/* Wait up to one second for reset to complete. */
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timeout = jiffies + 1 * HZ;
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while (time_before(jiffies, timeout)) {
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ret = REG_READ(REG_GLOBAL, 0x00);
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if ((ret & 0xc800) == 0xc800)
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break;
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usleep_range(1000, 2000);
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}
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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/* Enable ports not under DSA, e.g. WAN port */
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for (i = 0; i < 8; i++) {
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if (dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i))
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continue;
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ret = REG_READ(REG_PORT(i), 0x04);
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REG_WRITE(REG_PORT(i), 0x04, ret | 0x03);
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}
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return 0;
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}
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static int mv88e6171_setup_global(struct dsa_switch *ds)
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{
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int ret;
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int i;
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/* Disable the PHY polling unit (since there won't be any
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* external PHYs to poll), don't discard packets with
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* excessive collisions, and mask all interrupt sources.
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*/
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REG_WRITE(REG_GLOBAL, 0x04, 0x0000);
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/* Set the default address aging time to 5 minutes, and
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* enable address learn messages to be sent to all message
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* ports.
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*/
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REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
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/* Configure the priority mapping registers. */
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ret = mv88e6xxx_config_prio(ds);
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if (ret < 0)
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return ret;
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/* Configure the upstream port, and configure the upstream
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* port as the port to which ingress and egress monitor frames
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* are to be sent.
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*/
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if (REG_READ(REG_PORT(0), 0x03) == 0x1710)
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REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1111));
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else
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REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));
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/* Disable remote management for now, and set the switch's
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* DSA device number.
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*/
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REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
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/* Send all frames with destination addresses matching
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* 01:80:c2:00:00:2x to the CPU port.
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*/
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REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);
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/* Send all frames with destination addresses matching
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* 01:80:c2:00:00:0x to the CPU port.
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*/
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REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
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/* Disable the loopback filter, disable flow control
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* messages, disable flood broadcast override, disable
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* removing of provider tags, disable ATU age violation
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* interrupts, disable tag flow control, force flow
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* control priority to the highest, and send all special
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* multicast frames to the CPU at the highest priority.
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*/
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REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
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/* Program the DSA routing table. */
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for (i = 0; i < 32; i++) {
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int nexthop;
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nexthop = 0x1f;
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if (i != ds->index && i < ds->dst->pd->nr_chips)
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nexthop = ds->pd->rtable[i] & 0x1f;
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REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
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}
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/* Clear all trunk masks. */
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for (i = 0; i < 8; i++)
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REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff);
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/* Clear all trunk mappings. */
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for (i = 0; i < 16; i++)
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REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
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/* Disable ingress rate limiting by resetting all ingress
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* rate limit registers to their initial state.
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*/
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for (i = 0; i < 6; i++)
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REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));
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/* Initialise cross-chip port VLAN table to reset defaults. */
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REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);
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/* Clear the priority override table. */
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for (i = 0; i < 16; i++)
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REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));
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/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
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return 0;
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}
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static int mv88e6171_setup_port(struct dsa_switch *ds, int p)
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{
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int addr = REG_PORT(p);
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u16 val;
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/* MAC Forcing register: don't force link, speed, duplex
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* or flow control state to any particular values on physical
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* ports, but force the CPU port and all DSA ports to 1000 Mb/s
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* full duplex.
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*/
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val = REG_READ(addr, 0x01);
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if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
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REG_WRITE(addr, 0x01, val | 0x003e);
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else
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REG_WRITE(addr, 0x01, val | 0x0003);
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/* Do not limit the period of time that this port can be
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* paused for by the remote end or the period of time that
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* this port can pause the remote end.
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*/
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REG_WRITE(addr, 0x02, 0x0000);
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/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
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* disable Header mode, enable IGMP/MLD snooping, disable VLAN
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* tunneling, determine priority by looking at 802.1p and IP
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* priority fields (IP prio has precedence), and set STP state
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* to Forwarding.
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*
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* If this is the CPU link, use DSA or EDSA tagging depending
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* on which tagging mode was configured.
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*
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* If this is a link to another switch, use DSA tagging mode.
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*
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* If this is the upstream port for this switch, enable
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* forwarding of unknown unicasts and multicasts.
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*/
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val = 0x0433;
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if (dsa_is_cpu_port(ds, p)) {
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if (ds->dst->tag_protocol == htons(ETH_P_EDSA))
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val |= 0x3300;
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else
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val |= 0x0100;
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}
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if (ds->dsa_port_mask & (1 << p))
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val |= 0x0100;
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if (p == dsa_upstream_port(ds))
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val |= 0x000c;
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REG_WRITE(addr, 0x04, val);
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/* Port Control 1: disable trunking. Also, if this is the
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* CPU port, enable learn messages to be sent to this port.
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*/
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REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
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/* Port based VLAN map: give each port its own address
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* database, allow the CPU port to talk to each of the 'real'
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* ports, and allow each of the 'real' ports to only talk to
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* the upstream port.
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*/
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val = (p & 0xf) << 12;
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if (dsa_is_cpu_port(ds, p))
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val |= ds->phys_port_mask;
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else
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val |= 1 << dsa_upstream_port(ds);
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REG_WRITE(addr, 0x06, val);
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/* Default VLAN ID and priority: don't set a default VLAN
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* ID, and set the default packet priority to zero.
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*/
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REG_WRITE(addr, 0x07, 0x0000);
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/* Port Control 2: don't force a good FCS, set the maximum
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* frame size to 10240 bytes, don't let the switch add or
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* strip 802.1q tags, don't discard tagged or untagged frames
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* on this port, do a destination address lookup on all
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* received packets as usual, disable ARP mirroring and don't
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* send a copy of all transmitted/received frames on this port
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* to the CPU.
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*/
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REG_WRITE(addr, 0x08, 0x2080);
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/* Egress rate control: disable egress rate control. */
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REG_WRITE(addr, 0x09, 0x0001);
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/* Egress rate control 2: disable egress rate control. */
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REG_WRITE(addr, 0x0a, 0x0000);
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/* Port Association Vector: when learning source addresses
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* of packets, add the address to the address database using
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* a port bitmap that has only the bit for this port set and
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* the other bits clear.
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*/
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REG_WRITE(addr, 0x0b, 1 << p);
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/* Port ATU control: disable limiting the number of address
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* database entries that this port is allowed to use.
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*/
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REG_WRITE(addr, 0x0c, 0x0000);
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/* Priority Override: disable DA, SA and VTU priority override. */
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REG_WRITE(addr, 0x0d, 0x0000);
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/* Port Ethertype: use the Ethertype DSA Ethertype value. */
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REG_WRITE(addr, 0x0f, ETH_P_EDSA);
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/* Tag Remap: use an identity 802.1p prio -> switch prio
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* mapping.
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*/
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REG_WRITE(addr, 0x18, 0x3210);
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/* Tag Remap 2: use an identity 802.1p prio -> switch prio
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* mapping.
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*/
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REG_WRITE(addr, 0x19, 0x7654);
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return 0;
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}
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static int mv88e6171_setup(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
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int i;
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int ret;
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mutex_init(&ps->smi_mutex);
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mutex_init(&ps->stats_mutex);
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ret = mv88e6171_switch_reset(ds);
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if (ret < 0)
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return ret;
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/* @@@ initialise vtu and atu */
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ret = mv88e6171_setup_global(ds);
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if (ret < 0)
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return ret;
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for (i = 0; i < 8; i++) {
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if (!(dsa_is_cpu_port(ds, i) || ds->phys_port_mask & (1 << i)))
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continue;
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ret = mv88e6171_setup_port(ds, i);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int mv88e6171_port_to_phy_addr(int port)
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{
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if (port >= 0 && port <= 4)
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return port;
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return -1;
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}
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static int
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mv88e6171_phy_read(struct dsa_switch *ds, int port, int regnum)
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{
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int addr = mv88e6171_port_to_phy_addr(port);
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return mv88e6xxx_phy_read(ds, addr, regnum);
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}
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static int
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mv88e6171_phy_write(struct dsa_switch *ds,
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int port, int regnum, u16 val)
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{
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int addr = mv88e6171_port_to_phy_addr(port);
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return mv88e6xxx_phy_write(ds, addr, regnum, val);
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}
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static struct mv88e6xxx_hw_stat mv88e6171_hw_stats[] = {
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{ "in_good_octets", 8, 0x00, },
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{ "in_bad_octets", 4, 0x02, },
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{ "in_unicast", 4, 0x04, },
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{ "in_broadcasts", 4, 0x06, },
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{ "in_multicasts", 4, 0x07, },
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{ "in_pause", 4, 0x16, },
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{ "in_undersize", 4, 0x18, },
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{ "in_fragments", 4, 0x19, },
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{ "in_oversize", 4, 0x1a, },
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{ "in_jabber", 4, 0x1b, },
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{ "in_rx_error", 4, 0x1c, },
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{ "in_fcs_error", 4, 0x1d, },
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{ "out_octets", 8, 0x0e, },
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{ "out_unicast", 4, 0x10, },
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{ "out_broadcasts", 4, 0x13, },
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{ "out_multicasts", 4, 0x12, },
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{ "out_pause", 4, 0x15, },
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{ "excessive", 4, 0x11, },
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{ "collisions", 4, 0x1e, },
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{ "deferred", 4, 0x05, },
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{ "single", 4, 0x14, },
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{ "multiple", 4, 0x17, },
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{ "out_fcs_error", 4, 0x03, },
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{ "late", 4, 0x1f, },
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{ "hist_64bytes", 4, 0x08, },
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{ "hist_65_127bytes", 4, 0x09, },
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{ "hist_128_255bytes", 4, 0x0a, },
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{ "hist_256_511bytes", 4, 0x0b, },
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{ "hist_512_1023bytes", 4, 0x0c, },
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{ "hist_1024_max_bytes", 4, 0x0d, },
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};
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static void
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mv88e6171_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
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{
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mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6171_hw_stats),
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mv88e6171_hw_stats, port, data);
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}
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static void
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mv88e6171_get_ethtool_stats(struct dsa_switch *ds,
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int port, uint64_t *data)
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{
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mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6171_hw_stats),
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mv88e6171_hw_stats, port, data);
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}
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static int mv88e6171_get_sset_count(struct dsa_switch *ds)
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{
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return ARRAY_SIZE(mv88e6171_hw_stats);
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}
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struct dsa_switch_driver mv88e6171_switch_driver = {
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.tag_protocol = DSA_TAG_PROTO_DSA,
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.priv_size = sizeof(struct mv88e6xxx_priv_state),
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.probe = mv88e6171_probe,
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.setup = mv88e6171_setup,
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.set_addr = mv88e6xxx_set_addr_indirect,
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.phy_read = mv88e6171_phy_read,
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.phy_write = mv88e6171_phy_write,
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.poll_link = mv88e6xxx_poll_link,
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.get_strings = mv88e6171_get_strings,
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.get_ethtool_stats = mv88e6171_get_ethtool_stats,
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.get_sset_count = mv88e6171_get_sset_count,
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};
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MODULE_ALIAS("platform:mv88e6171");
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