forked from Minki/linux
a941c50340
The drivers on da8xx/omapl EVMs do not utilize all the channels and slots provided by EDMA. Some of these are better utilitzed by the DSP on the SoC for speeding up codec operations. Reserve these channels/slots for the DSP. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
659 lines
15 KiB
C
659 lines
15 KiB
C
/*
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* DA8XX/OMAP L1XX platform device data
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*
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* Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
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* Derived from code that was:
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* Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/serial_8250.h>
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#include <mach/cputype.h>
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#include <mach/common.h>
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#include <mach/time.h>
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#include <mach/da8xx.h>
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#include <mach/cpuidle.h>
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#include "clock.h"
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#define DA8XX_TPCC_BASE 0x01c00000
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#define DA850_TPCC1_BASE 0x01e30000
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#define DA8XX_TPTC0_BASE 0x01c08000
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#define DA8XX_TPTC1_BASE 0x01c08400
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#define DA850_TPTC2_BASE 0x01e38000
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#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
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#define DA8XX_I2C0_BASE 0x01c22000
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#define DA8XX_RTC_BASE 0x01C23000
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#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
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#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
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#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
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#define DA8XX_EMAC_MDIO_BASE 0x01e24000
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#define DA8XX_GPIO_BASE 0x01e26000
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#define DA8XX_I2C1_BASE 0x01e28000
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#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
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#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
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#define DA8XX_EMAC_RAM_OFFSET 0x0000
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#define DA8XX_MDIO_REG_OFFSET 0x4000
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#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
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void __iomem *da8xx_syscfg0_base;
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void __iomem *da8xx_syscfg1_base;
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static struct plat_serial8250_port da8xx_serial_pdata[] = {
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{
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.mapbase = DA8XX_UART0_BASE,
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.irq = IRQ_DA8XX_UARTINT0,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
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UPF_IOREMAP,
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.iotype = UPIO_MEM,
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.regshift = 2,
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},
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{
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.mapbase = DA8XX_UART1_BASE,
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.irq = IRQ_DA8XX_UARTINT1,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
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UPF_IOREMAP,
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.iotype = UPIO_MEM,
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.regshift = 2,
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},
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{
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.mapbase = DA8XX_UART2_BASE,
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.irq = IRQ_DA8XX_UARTINT2,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
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UPF_IOREMAP,
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.iotype = UPIO_MEM,
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.regshift = 2,
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},
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{
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.flags = 0,
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},
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};
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struct platform_device da8xx_serial_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = da8xx_serial_pdata,
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},
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};
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static const s8 da8xx_queue_tc_mapping[][2] = {
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/* {event queue no, TC no} */
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{0, 0},
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{1, 1},
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{-1, -1}
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};
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static const s8 da8xx_queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 3},
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{1, 7},
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{-1, -1}
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};
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static const s8 da850_queue_tc_mapping[][2] = {
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/* {event queue no, TC no} */
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{0, 0},
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{-1, -1}
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};
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static const s8 da850_queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 3},
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{-1, -1}
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};
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static struct edma_soc_info da830_edma_cc0_info = {
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.n_channel = 32,
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.n_region = 4,
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.n_slot = 128,
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.n_tc = 2,
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.n_cc = 1,
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.queue_tc_mapping = da8xx_queue_tc_mapping,
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.queue_priority_mapping = da8xx_queue_priority_mapping,
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};
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static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
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&da830_edma_cc0_info,
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};
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static struct edma_soc_info da850_edma_cc_info[] = {
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{
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.n_channel = 32,
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.n_region = 4,
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.n_slot = 128,
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.n_tc = 2,
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.n_cc = 1,
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.queue_tc_mapping = da8xx_queue_tc_mapping,
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.queue_priority_mapping = da8xx_queue_priority_mapping,
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},
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{
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.n_channel = 32,
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.n_region = 4,
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.n_slot = 128,
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.n_tc = 1,
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.n_cc = 1,
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.queue_tc_mapping = da850_queue_tc_mapping,
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.queue_priority_mapping = da850_queue_priority_mapping,
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},
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};
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static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
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&da850_edma_cc_info[0],
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&da850_edma_cc_info[1],
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};
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static struct resource da830_edma_resources[] = {
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{
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.name = "edma_cc0",
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.start = DA8XX_TPCC_BASE,
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.end = DA8XX_TPCC_BASE + SZ_32K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma_tc0",
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.start = DA8XX_TPTC0_BASE,
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.end = DA8XX_TPTC0_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma_tc1",
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.start = DA8XX_TPTC1_BASE,
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.end = DA8XX_TPTC1_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma0",
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.start = IRQ_DA8XX_CCINT0,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "edma0_err",
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.start = IRQ_DA8XX_CCERRINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource da850_edma_resources[] = {
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{
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.name = "edma_cc0",
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.start = DA8XX_TPCC_BASE,
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.end = DA8XX_TPCC_BASE + SZ_32K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma_tc0",
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.start = DA8XX_TPTC0_BASE,
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.end = DA8XX_TPTC0_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma_tc1",
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.start = DA8XX_TPTC1_BASE,
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.end = DA8XX_TPTC1_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma_cc1",
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.start = DA850_TPCC1_BASE,
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.end = DA850_TPCC1_BASE + SZ_32K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma_tc2",
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.start = DA850_TPTC2_BASE,
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.end = DA850_TPTC2_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma0",
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.start = IRQ_DA8XX_CCINT0,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "edma0_err",
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.start = IRQ_DA8XX_CCERRINT,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "edma1",
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.start = IRQ_DA850_CCINT1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "edma1_err",
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.start = IRQ_DA850_CCERRINT1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device da830_edma_device = {
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.name = "edma",
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.id = -1,
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.dev = {
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.platform_data = da830_edma_info,
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},
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.num_resources = ARRAY_SIZE(da830_edma_resources),
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.resource = da830_edma_resources,
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};
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static struct platform_device da850_edma_device = {
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.name = "edma",
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.id = -1,
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.dev = {
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.platform_data = da850_edma_info,
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},
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.num_resources = ARRAY_SIZE(da850_edma_resources),
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.resource = da850_edma_resources,
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};
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int __init da830_register_edma(struct edma_rsv_info *rsv)
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{
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da830_edma_cc0_info.rsv = rsv;
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return platform_device_register(&da830_edma_device);
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}
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int __init da850_register_edma(struct edma_rsv_info *rsv[2])
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{
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if (rsv) {
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da850_edma_cc_info[0].rsv = rsv[0];
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da850_edma_cc_info[1].rsv = rsv[1];
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}
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return platform_device_register(&da850_edma_device);
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}
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static struct resource da8xx_i2c_resources0[] = {
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{
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.start = DA8XX_I2C0_BASE,
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.end = DA8XX_I2C0_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_DA8XX_I2CINT0,
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.end = IRQ_DA8XX_I2CINT0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device da8xx_i2c_device0 = {
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.name = "i2c_davinci",
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.id = 1,
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.num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
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.resource = da8xx_i2c_resources0,
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};
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static struct resource da8xx_i2c_resources1[] = {
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{
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.start = DA8XX_I2C1_BASE,
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.end = DA8XX_I2C1_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_DA8XX_I2CINT1,
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.end = IRQ_DA8XX_I2CINT1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device da8xx_i2c_device1 = {
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.name = "i2c_davinci",
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.id = 2,
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.num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
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.resource = da8xx_i2c_resources1,
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};
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int __init da8xx_register_i2c(int instance,
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struct davinci_i2c_platform_data *pdata)
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{
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struct platform_device *pdev;
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if (instance == 0)
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pdev = &da8xx_i2c_device0;
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else if (instance == 1)
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pdev = &da8xx_i2c_device1;
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else
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return -EINVAL;
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pdev->dev.platform_data = pdata;
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return platform_device_register(pdev);
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}
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static struct resource da8xx_watchdog_resources[] = {
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{
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.start = DA8XX_WDOG_BASE,
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.end = DA8XX_WDOG_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device da8xx_wdt_device = {
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.name = "watchdog",
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.id = -1,
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.num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
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.resource = da8xx_watchdog_resources,
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};
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int __init da8xx_register_watchdog(void)
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{
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return platform_device_register(&da8xx_wdt_device);
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}
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static struct resource da8xx_emac_resources[] = {
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{
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.start = DA8XX_EMAC_CPPI_PORT_BASE,
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.end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
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.end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_DA8XX_C0_RX_PULSE,
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.end = IRQ_DA8XX_C0_RX_PULSE,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_DA8XX_C0_TX_PULSE,
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.end = IRQ_DA8XX_C0_TX_PULSE,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_DA8XX_C0_MISC_PULSE,
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.end = IRQ_DA8XX_C0_MISC_PULSE,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct emac_platform_data da8xx_emac_pdata = {
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.ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
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.ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
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.ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
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.mdio_reg_offset = DA8XX_MDIO_REG_OFFSET,
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.ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
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.version = EMAC_VERSION_2,
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};
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static struct platform_device da8xx_emac_device = {
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.name = "davinci_emac",
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.id = 1,
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.dev = {
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.platform_data = &da8xx_emac_pdata,
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},
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.num_resources = ARRAY_SIZE(da8xx_emac_resources),
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.resource = da8xx_emac_resources,
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};
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int __init da8xx_register_emac(void)
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{
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return platform_device_register(&da8xx_emac_device);
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}
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static struct resource da830_mcasp1_resources[] = {
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{
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.name = "mcasp1",
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.start = DAVINCI_DA830_MCASP1_REG_BASE,
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.end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
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.flags = IORESOURCE_MEM,
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},
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/* TX event */
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{
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.start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
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.end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
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.flags = IORESOURCE_DMA,
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},
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/* RX event */
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{
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.start = DAVINCI_DA830_DMA_MCASP1_AREVT,
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.end = DAVINCI_DA830_DMA_MCASP1_AREVT,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device da830_mcasp1_device = {
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.name = "davinci-mcasp",
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.id = 1,
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.num_resources = ARRAY_SIZE(da830_mcasp1_resources),
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.resource = da830_mcasp1_resources,
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};
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static struct resource da850_mcasp_resources[] = {
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{
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.name = "mcasp",
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.start = DAVINCI_DA8XX_MCASP0_REG_BASE,
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.end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
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.flags = IORESOURCE_MEM,
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},
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/* TX event */
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{
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.start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
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.end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
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.flags = IORESOURCE_DMA,
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},
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/* RX event */
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{
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.start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
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.end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device da850_mcasp_device = {
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.name = "davinci-mcasp",
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.id = 0,
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.num_resources = ARRAY_SIZE(da850_mcasp_resources),
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.resource = da850_mcasp_resources,
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};
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void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
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{
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/* DA830/OMAP-L137 has 3 instances of McASP */
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if (cpu_is_davinci_da830() && id == 1) {
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da830_mcasp1_device.dev.platform_data = pdata;
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platform_device_register(&da830_mcasp1_device);
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} else if (cpu_is_davinci_da850()) {
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da850_mcasp_device.dev.platform_data = pdata;
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platform_device_register(&da850_mcasp_device);
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}
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}
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static const struct display_panel disp_panel = {
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QVGA,
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16,
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16,
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COLOR_ACTIVE,
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};
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static struct lcd_ctrl_config lcd_cfg = {
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&disp_panel,
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.ac_bias = 255,
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.ac_bias_intrpt = 0,
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.dma_burst_sz = 16,
|
|
.bpp = 16,
|
|
.fdd = 255,
|
|
.tft_alt_mode = 0,
|
|
.stn_565_mode = 0,
|
|
.mono_8bit_mode = 0,
|
|
.invert_line_clock = 1,
|
|
.invert_frm_clock = 1,
|
|
.sync_edge = 0,
|
|
.sync_ctrl = 1,
|
|
.raster_order = 0,
|
|
};
|
|
|
|
struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
|
|
.manu_name = "sharp",
|
|
.controller_data = &lcd_cfg,
|
|
.type = "Sharp_LCD035Q3DG01",
|
|
};
|
|
|
|
struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
|
|
.manu_name = "sharp",
|
|
.controller_data = &lcd_cfg,
|
|
.type = "Sharp_LK043T1DG01",
|
|
};
|
|
|
|
static struct resource da8xx_lcdc_resources[] = {
|
|
[0] = { /* registers */
|
|
.start = DA8XX_LCD_CNTRL_BASE,
|
|
.end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = { /* interrupt */
|
|
.start = IRQ_DA8XX_LCDINT,
|
|
.end = IRQ_DA8XX_LCDINT,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da8xx_lcdc_device = {
|
|
.name = "da8xx_lcdc",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
|
|
.resource = da8xx_lcdc_resources,
|
|
};
|
|
|
|
int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
|
|
{
|
|
da8xx_lcdc_device.dev.platform_data = pdata;
|
|
return platform_device_register(&da8xx_lcdc_device);
|
|
}
|
|
|
|
static struct resource da8xx_mmcsd0_resources[] = {
|
|
{ /* registers */
|
|
.start = DA8XX_MMCSD0_BASE,
|
|
.end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* interrupt */
|
|
.start = IRQ_DA8XX_MMCSDINT0,
|
|
.end = IRQ_DA8XX_MMCSDINT0,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{ /* DMA RX */
|
|
.start = EDMA_CTLR_CHAN(0, 16),
|
|
.end = EDMA_CTLR_CHAN(0, 16),
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
{ /* DMA TX */
|
|
.start = EDMA_CTLR_CHAN(0, 17),
|
|
.end = EDMA_CTLR_CHAN(0, 17),
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da8xx_mmcsd0_device = {
|
|
.name = "davinci_mmc",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
|
|
.resource = da8xx_mmcsd0_resources,
|
|
};
|
|
|
|
int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
|
|
{
|
|
da8xx_mmcsd0_device.dev.platform_data = config;
|
|
return platform_device_register(&da8xx_mmcsd0_device);
|
|
}
|
|
|
|
static struct resource da8xx_rtc_resources[] = {
|
|
{
|
|
.start = DA8XX_RTC_BASE,
|
|
.end = DA8XX_RTC_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* timer irq */
|
|
.start = IRQ_DA8XX_RTC,
|
|
.end = IRQ_DA8XX_RTC,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{ /* alarm irq */
|
|
.start = IRQ_DA8XX_RTC,
|
|
.end = IRQ_DA8XX_RTC,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device da8xx_rtc_device = {
|
|
.name = "omap_rtc",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(da8xx_rtc_resources),
|
|
.resource = da8xx_rtc_resources,
|
|
};
|
|
|
|
int da8xx_register_rtc(void)
|
|
{
|
|
int ret;
|
|
void __iomem *base;
|
|
|
|
base = ioremap(DA8XX_RTC_BASE, SZ_4K);
|
|
if (WARN_ON(!base))
|
|
return -ENOMEM;
|
|
|
|
/* Unlock the rtc's registers */
|
|
__raw_writel(0x83e70b13, base + 0x6c);
|
|
__raw_writel(0x95a4f1e0, base + 0x70);
|
|
|
|
iounmap(base);
|
|
|
|
ret = platform_device_register(&da8xx_rtc_device);
|
|
if (!ret)
|
|
/* Atleast on DA850, RTC is a wakeup source */
|
|
device_init_wakeup(&da8xx_rtc_device.dev, true);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __iomem *da8xx_ddr2_ctlr_base;
|
|
void __iomem * __init da8xx_get_mem_ctlr(void)
|
|
{
|
|
if (da8xx_ddr2_ctlr_base)
|
|
return da8xx_ddr2_ctlr_base;
|
|
|
|
da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
|
|
if (!da8xx_ddr2_ctlr_base)
|
|
pr_warning("%s: Unable to map DDR2 controller", __func__);
|
|
|
|
return da8xx_ddr2_ctlr_base;
|
|
}
|
|
|
|
static struct resource da8xx_cpuidle_resources[] = {
|
|
{
|
|
.start = DA8XX_DDR2_CTL_BASE,
|
|
.end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
/* DA8XX devices support DDR2 power down */
|
|
static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
|
|
.ddr2_pdown = 1,
|
|
};
|
|
|
|
|
|
static struct platform_device da8xx_cpuidle_device = {
|
|
.name = "cpuidle-davinci",
|
|
.num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
|
|
.resource = da8xx_cpuidle_resources,
|
|
.dev = {
|
|
.platform_data = &da8xx_cpuidle_pdata,
|
|
},
|
|
};
|
|
|
|
int __init da8xx_register_cpuidle(void)
|
|
{
|
|
da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
|
|
|
|
return platform_device_register(&da8xx_cpuidle_device);
|
|
}
|