forked from Minki/linux
3b758a6840
In aiutils.c the selected core was maintained by its index number. This is obsolete using BCMA functions so several functions using that index have been removed. Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Alwin Beukers <alwin@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
301 lines
9.6 KiB
C
301 lines
9.6 KiB
C
/*
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* Copyright (c) 2011 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _BRCM_AIUTILS_H_
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#define _BRCM_AIUTILS_H_
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#include <linux/bcma/bcma.h>
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#include "types.h"
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/*
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* SOC Interconnect Address Map.
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* All regions may not exist on all chips.
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*/
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/* each core gets 4Kbytes for registers */
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#define SI_CORE_SIZE 0x1000
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/*
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* Max cores (this is arbitrary, for software
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* convenience and could be changed if we
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* make any larger chips
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*/
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#define SI_MAXCORES 16
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/* Client Mode sb2pcitranslation2 size in bytes */
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#define SI_PCI_DMA_SZ 0x40000000
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/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
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#define SI_PCIE_DMA_H32 0x80000000
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/* chipcommon being the first core: */
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#define SI_CC_IDX 0
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/* SOC Interconnect types (aka chip types) */
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#define SOCI_AI 1
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/* A register that is common to all cores to
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* communicate w/PMU regarding clock control.
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*/
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#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
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/* clk_ctl_st register */
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#define CCS_FORCEALP 0x00000001 /* force ALP request */
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#define CCS_FORCEHT 0x00000002 /* force HT request */
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#define CCS_FORCEILP 0x00000004 /* force ILP request */
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#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
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#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
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#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
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#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
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#define CCS_ERSRC_REQ_SHIFT 8
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#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
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#define CCS_HTAVAIL 0x00020000 /* HT is available */
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#define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
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#define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
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#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
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#define CCS_ERSRC_STS_SHIFT 24
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/* HT avail in chipc and pcmcia on 4328a0 */
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#define CCS0_HTAVAIL 0x00010000
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/* ALP avail in chipc and pcmcia on 4328a0 */
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#define CCS0_ALPAVAIL 0x00020000
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/* Not really related to SOC Interconnect, but a couple of software
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* conventions for the use the flash space:
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*/
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/* Minumum amount of flash we support */
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#define FLASH_MIN 0x00020000 /* Minimum flash size */
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#define CC_SROM_OTP 0x800 /* SROM/OTP address space */
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/* gpiotimerval */
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#define GPIO_ONTIME_SHIFT 16
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/* Fields in clkdiv */
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#define CLKD_OTP 0x000f0000
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#define CLKD_OTP_SHIFT 16
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/* Package IDs */
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#define BCM4717_PKG_ID 9 /* 4717 package id */
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#define BCM4718_PKG_ID 10 /* 4718 package id */
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#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
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/* these are router chips */
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#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
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#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
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#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
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/* dynamic clock control defines */
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#define LPOMINFREQ 25000 /* low power oscillator min */
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#define LPOMAXFREQ 43000 /* low power oscillator max */
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#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
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#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
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#define PCIMINFREQ 25000000 /* 25 MHz */
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#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
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#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
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#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
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/* clkctl xtal what flags */
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#define XTAL 0x1 /* primary crystal oscillator (2050) */
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#define PLL 0x2 /* main chip pll */
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/* clkctl clk mode */
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#define CLK_FAST 0 /* force fast (pll) clock */
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#define CLK_DYNAMIC 2 /* enable dynamic clock control */
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/* GPIO usage priorities */
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#define GPIO_DRV_PRIORITY 0 /* Driver */
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#define GPIO_APP_PRIORITY 1 /* Application */
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#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
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* reservation
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*/
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/* GPIO pull up/down */
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#define GPIO_PULLUP 0
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#define GPIO_PULLDN 1
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/* GPIO event regtype */
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#define GPIO_REGEVT 0 /* GPIO register event */
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#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
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#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
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/* device path */
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#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
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/* SI routine enumeration: to be used by update function with multiple hooks */
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#define SI_DOATTACH 1
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#define SI_PCIDOWN 2
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#define SI_PCIUP 3
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/*
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* Data structure to export all chip specific common variables
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* public (read-only) portion of aiutils handle returned by si_attach()
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*/
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struct si_pub {
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uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
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uint buscorerev; /* buscore rev */
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int ccrev; /* chip common core rev */
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u32 cccaps; /* chip common capabilities */
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int pmurev; /* pmu core rev */
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u32 pmucaps; /* pmu capabilities */
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uint boardtype; /* board type */
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uint boardvendor; /* board vendor */
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uint chip; /* chip number */
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uint chiprev; /* chip revision */
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uint chippkg; /* chip package option */
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};
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struct pci_dev;
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struct gpioh_item {
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void *arg;
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bool level;
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void (*handler) (u32 stat, void *arg);
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u32 event;
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struct gpioh_item *next;
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};
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/* misc si info needed by some of the routines */
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struct si_info {
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struct si_pub pub; /* back plane public state (must be first) */
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struct bcma_bus *icbus; /* handle to soc interconnect bus */
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struct pci_dev *pcibus; /* handle to pci bus */
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uint dev_coreid; /* the core provides driver functions */
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void *intr_arg; /* interrupt callback function arg */
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u32 (*intrsoff_fn) (void *intr_arg); /* turns chip interrupts off */
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/* restore chip interrupts */
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void (*intrsrestore_fn) (void *intr_arg, u32 arg);
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/* check if interrupts are enabled */
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bool (*intrsenabled_fn) (void *intr_arg);
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struct pcicore_info *pch; /* PCI/E core handle */
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struct list_head var_list; /* list of srom variables */
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void __iomem *curmap; /* current regs va */
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void __iomem *regs[SI_MAXCORES]; /* other regs va */
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u32 chipst; /* chip status */
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uint curidx; /* current core index */
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uint buscoreidx; /* buscore index */
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uint numcores; /* # discovered cores */
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uint coreid[SI_MAXCORES]; /* id of each core */
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u32 coresba[SI_MAXCORES]; /* backplane address of each core */
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void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
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u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
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u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
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u32 coresba2_size[SI_MAXCORES]; /* second address space size */
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void *curwrap; /* current wrapper va */
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void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
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u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
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u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
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u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
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u32 oob_router; /* oob router registers for axi */
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};
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/*
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* Many of the routines below take an 'sih' handle as their first arg.
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* Allocate this by calling si_attach(). Free it by calling si_detach().
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* At any one time, the sih is logically focused on one particular si core
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* (the "current core").
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* Use si_setcore() or si_setcoreidx() to change the association to another core
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*/
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/* AMBA Interconnect exported externs */
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extern struct bcma_device *ai_findcore(struct si_pub *sih,
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u16 coreid, u16 coreunit);
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extern u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
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/* === exported functions === */
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extern struct si_pub *ai_attach(struct bcma_bus *pbus);
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extern void ai_detach(struct si_pub *sih);
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extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
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extern void ai_pci_setup(struct si_pub *sih, uint coremask);
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extern void ai_clkctl_init(struct si_pub *sih);
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extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
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extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
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extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
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extern bool ai_deviceremoved(struct si_pub *sih);
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extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
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u8 priority);
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/* OTP status */
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extern bool ai_is_otp_disabled(struct si_pub *sih);
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/* SPROM availability */
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extern bool ai_is_sprom_available(struct si_pub *sih);
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extern void ai_pci_sleep(struct si_pub *sih);
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extern void ai_pci_down(struct si_pub *sih);
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extern void ai_pci_up(struct si_pub *sih);
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extern int ai_pci_fixcfg(struct si_pub *sih);
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extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
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/* Enable Ex-PA for 4313 */
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extern void ai_epa_4313war(struct si_pub *sih);
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static inline uint ai_get_buscoretype(struct si_pub *sih)
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{
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return sih->buscoretype;
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}
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static inline uint ai_get_buscorerev(struct si_pub *sih)
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{
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return sih->buscorerev;
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}
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static inline int ai_get_ccrev(struct si_pub *sih)
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{
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return sih->ccrev;
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}
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static inline u32 ai_get_cccaps(struct si_pub *sih)
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{
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return sih->cccaps;
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}
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static inline int ai_get_pmurev(struct si_pub *sih)
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{
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return sih->pmurev;
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}
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static inline u32 ai_get_pmucaps(struct si_pub *sih)
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{
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return sih->pmucaps;
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}
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static inline uint ai_get_boardtype(struct si_pub *sih)
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{
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return sih->boardtype;
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}
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static inline uint ai_get_boardvendor(struct si_pub *sih)
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{
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return sih->boardvendor;
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}
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static inline uint ai_get_chip_id(struct si_pub *sih)
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{
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return sih->chip;
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}
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static inline uint ai_get_chiprev(struct si_pub *sih)
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{
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return sih->chiprev;
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}
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static inline uint ai_get_chippkg(struct si_pub *sih)
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{
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return sih->chippkg;
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}
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#endif /* _BRCM_AIUTILS_H_ */
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