forked from Minki/linux
781 lines
19 KiB
C
781 lines
19 KiB
C
/*
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* drivers/spi/spi-fsl-dspi.c
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Freescale DSPI driver
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* This file contains a driver for the Freescale DSPI
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/sched.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/time.h>
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#define DRIVER_NAME "fsl-dspi"
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#define TRAN_STATE_RX_VOID 0x01
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#define TRAN_STATE_TX_VOID 0x02
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#define TRAN_STATE_WORD_ODD_NUM 0x04
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#define DSPI_FIFO_SIZE 4
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#define SPI_MCR 0x00
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#define SPI_MCR_MASTER (1 << 31)
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#define SPI_MCR_PCSIS (0x3F << 16)
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#define SPI_MCR_CLR_TXF (1 << 11)
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#define SPI_MCR_CLR_RXF (1 << 10)
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#define SPI_TCR 0x08
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#define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16)
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#define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
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#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
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#define SPI_CTAR_CPOL(x) ((x) << 26)
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#define SPI_CTAR_CPHA(x) ((x) << 25)
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#define SPI_CTAR_LSBFE(x) ((x) << 24)
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#define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
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#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
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#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
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#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
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#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
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#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
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#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
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#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
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#define SPI_CTAR_SCALE_BITS 0xf
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#define SPI_CTAR0_SLAVE 0x0c
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#define SPI_SR 0x2c
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#define SPI_SR_EOQF 0x10000000
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#define SPI_SR_TCFQF 0x80000000
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#define SPI_RSER 0x30
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#define SPI_RSER_EOQFE 0x10000000
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#define SPI_RSER_TCFQE 0x80000000
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#define SPI_PUSHR 0x34
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#define SPI_PUSHR_CONT (1 << 31)
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#define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28)
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#define SPI_PUSHR_EOQ (1 << 27)
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#define SPI_PUSHR_CTCNT (1 << 26)
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#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
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#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
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#define SPI_PUSHR_SLAVE 0x34
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#define SPI_POPR 0x38
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#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
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#define SPI_TXFR0 0x3c
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#define SPI_TXFR1 0x40
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#define SPI_TXFR2 0x44
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#define SPI_TXFR3 0x48
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#define SPI_RXFR0 0x7c
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#define SPI_RXFR1 0x80
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#define SPI_RXFR2 0x84
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#define SPI_RXFR3 0x88
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#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
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#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
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#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
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#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
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#define SPI_CS_INIT 0x01
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#define SPI_CS_ASSERT 0x02
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#define SPI_CS_DROP 0x04
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#define SPI_TCR_TCNT_MAX 0x10000
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struct chip_data {
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u32 mcr_val;
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u32 ctar_val;
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u16 void_write_data;
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};
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enum dspi_trans_mode {
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DSPI_EOQ_MODE = 0,
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DSPI_TCFQ_MODE,
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};
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struct fsl_dspi_devtype_data {
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enum dspi_trans_mode trans_mode;
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u8 max_clock_factor;
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};
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static const struct fsl_dspi_devtype_data vf610_data = {
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.trans_mode = DSPI_EOQ_MODE,
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.max_clock_factor = 2,
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};
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static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
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.trans_mode = DSPI_TCFQ_MODE,
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.max_clock_factor = 8,
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};
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static const struct fsl_dspi_devtype_data ls2085a_data = {
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.trans_mode = DSPI_TCFQ_MODE,
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.max_clock_factor = 8,
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};
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struct fsl_dspi {
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struct spi_master *master;
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struct platform_device *pdev;
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struct regmap *regmap;
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int irq;
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struct clk *clk;
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struct spi_transfer *cur_transfer;
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struct spi_message *cur_msg;
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struct chip_data *cur_chip;
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size_t len;
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void *tx;
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void *tx_end;
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void *rx;
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void *rx_end;
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char dataflags;
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u8 cs;
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u16 void_write_data;
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u32 cs_change;
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struct fsl_dspi_devtype_data *devtype_data;
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wait_queue_head_t waitq;
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u32 waitflags;
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u32 spi_tcnt;
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};
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static inline int is_double_byte_mode(struct fsl_dspi *dspi)
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{
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unsigned int val;
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regmap_read(dspi->regmap, SPI_CTAR(0), &val);
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return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
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}
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static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
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unsigned long clkrate)
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{
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/* Valid baud rate pre-scaler values */
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int pbr_tbl[4] = {2, 3, 5, 7};
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int brs[16] = { 2, 4, 6, 8,
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16, 32, 64, 128,
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256, 512, 1024, 2048,
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4096, 8192, 16384, 32768 };
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int scale_needed, scale, minscale = INT_MAX;
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int i, j;
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scale_needed = clkrate / speed_hz;
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if (clkrate % speed_hz)
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scale_needed++;
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for (i = 0; i < ARRAY_SIZE(brs); i++)
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for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
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scale = brs[i] * pbr_tbl[j];
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if (scale >= scale_needed) {
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if (scale < minscale) {
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minscale = scale;
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*br = i;
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*pbr = j;
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}
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break;
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}
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}
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if (minscale == INT_MAX) {
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pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
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speed_hz, clkrate);
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*pbr = ARRAY_SIZE(pbr_tbl) - 1;
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*br = ARRAY_SIZE(brs) - 1;
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}
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}
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static void ns_delay_scale(char *psc, char *sc, int delay_ns,
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unsigned long clkrate)
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{
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int pscale_tbl[4] = {1, 3, 5, 7};
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int scale_needed, scale, minscale = INT_MAX;
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int i, j;
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u32 remainder;
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scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
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&remainder);
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if (remainder)
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scale_needed++;
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for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
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for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
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scale = pscale_tbl[i] * (2 << j);
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if (scale >= scale_needed) {
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if (scale < minscale) {
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minscale = scale;
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*psc = i;
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*sc = j;
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}
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break;
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}
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}
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if (minscale == INT_MAX) {
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pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
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delay_ns, clkrate);
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*psc = ARRAY_SIZE(pscale_tbl) - 1;
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*sc = SPI_CTAR_SCALE_BITS;
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}
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}
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static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word)
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{
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u16 d16;
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if (!(dspi->dataflags & TRAN_STATE_TX_VOID))
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d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx;
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else
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d16 = dspi->void_write_data;
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dspi->tx += tx_word + 1;
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dspi->len -= tx_word + 1;
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return SPI_PUSHR_TXDATA(d16) |
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SPI_PUSHR_PCS(dspi->cs) |
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SPI_PUSHR_CTAS(0) |
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SPI_PUSHR_CONT;
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}
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static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word)
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{
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u16 d;
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unsigned int val;
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regmap_read(dspi->regmap, SPI_POPR, &val);
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d = SPI_POPR_RXDATA(val);
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if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
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rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d);
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dspi->rx += rx_word + 1;
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}
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static int dspi_eoq_write(struct fsl_dspi *dspi)
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{
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int tx_count = 0;
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int tx_word;
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u32 dspi_pushr = 0;
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tx_word = is_double_byte_mode(dspi);
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while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
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/* If we are in word mode, only have a single byte to transfer
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* switch to byte mode temporarily. Will switch back at the
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* end of the transfer.
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*/
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if (tx_word && (dspi->len == 1)) {
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dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
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regmap_update_bits(dspi->regmap, SPI_CTAR(0),
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SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
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tx_word = 0;
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}
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dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
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if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
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/* last transfer in the transfer */
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dspi_pushr |= SPI_PUSHR_EOQ;
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if ((dspi->cs_change) && (!dspi->len))
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dspi_pushr &= ~SPI_PUSHR_CONT;
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} else if (tx_word && (dspi->len == 1))
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dspi_pushr |= SPI_PUSHR_EOQ;
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regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
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tx_count++;
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}
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return tx_count * (tx_word + 1);
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}
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static int dspi_eoq_read(struct fsl_dspi *dspi)
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{
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int rx_count = 0;
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int rx_word = is_double_byte_mode(dspi);
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while ((dspi->rx < dspi->rx_end)
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&& (rx_count < DSPI_FIFO_SIZE)) {
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if (rx_word && (dspi->rx_end - dspi->rx) == 1)
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rx_word = 0;
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dspi_data_from_popr(dspi, rx_word);
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rx_count++;
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}
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return rx_count;
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}
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static int dspi_tcfq_write(struct fsl_dspi *dspi)
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{
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int tx_word;
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u32 dspi_pushr = 0;
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tx_word = is_double_byte_mode(dspi);
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if (tx_word && (dspi->len == 1)) {
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dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
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regmap_update_bits(dspi->regmap, SPI_CTAR(0),
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SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
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tx_word = 0;
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}
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dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
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if ((dspi->cs_change) && (!dspi->len))
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dspi_pushr &= ~SPI_PUSHR_CONT;
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regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
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return tx_word + 1;
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}
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static void dspi_tcfq_read(struct fsl_dspi *dspi)
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{
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int rx_word = is_double_byte_mode(dspi);
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if (rx_word && (dspi->rx_end - dspi->rx) == 1)
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rx_word = 0;
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dspi_data_from_popr(dspi, rx_word);
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}
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static int dspi_transfer_one_message(struct spi_master *master,
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struct spi_message *message)
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{
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struct fsl_dspi *dspi = spi_master_get_devdata(master);
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struct spi_device *spi = message->spi;
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struct spi_transfer *transfer;
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int status = 0;
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enum dspi_trans_mode trans_mode;
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u32 spi_tcr;
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regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
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dspi->spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
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message->actual_length = 0;
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list_for_each_entry(transfer, &message->transfers, transfer_list) {
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dspi->cur_transfer = transfer;
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dspi->cur_msg = message;
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dspi->cur_chip = spi_get_ctldata(spi);
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dspi->cs = spi->chip_select;
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dspi->cs_change = 0;
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if (list_is_last(&dspi->cur_transfer->transfer_list,
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&dspi->cur_msg->transfers) || transfer->cs_change)
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dspi->cs_change = 1;
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dspi->void_write_data = dspi->cur_chip->void_write_data;
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dspi->dataflags = 0;
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dspi->tx = (void *)transfer->tx_buf;
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dspi->tx_end = dspi->tx + transfer->len;
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dspi->rx = transfer->rx_buf;
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dspi->rx_end = dspi->rx + transfer->len;
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dspi->len = transfer->len;
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if (!dspi->rx)
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dspi->dataflags |= TRAN_STATE_RX_VOID;
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if (!dspi->tx)
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dspi->dataflags |= TRAN_STATE_TX_VOID;
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regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
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regmap_update_bits(dspi->regmap, SPI_MCR,
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SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
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SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
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regmap_write(dspi->regmap, SPI_CTAR(0),
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dspi->cur_chip->ctar_val);
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trans_mode = dspi->devtype_data->trans_mode;
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switch (trans_mode) {
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case DSPI_EOQ_MODE:
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regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
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dspi_eoq_write(dspi);
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break;
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case DSPI_TCFQ_MODE:
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regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
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dspi_tcfq_write(dspi);
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break;
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default:
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dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
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trans_mode);
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status = -EINVAL;
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goto out;
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}
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if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
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dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
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dspi->waitflags = 0;
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if (transfer->delay_usecs)
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udelay(transfer->delay_usecs);
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}
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out:
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message->status = status;
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spi_finalize_current_message(master);
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return status;
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}
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static int dspi_setup(struct spi_device *spi)
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{
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struct chip_data *chip;
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struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
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u32 cs_sck_delay = 0, sck_cs_delay = 0;
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unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
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unsigned char pasc = 0, asc = 0, fmsz = 0;
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unsigned long clkrate;
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if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
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fmsz = spi->bits_per_word - 1;
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} else {
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pr_err("Invalid wordsize\n");
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return -ENODEV;
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}
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/* Only alloc on first setup */
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chip = spi_get_ctldata(spi);
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if (chip == NULL) {
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chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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}
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of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
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&cs_sck_delay);
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of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
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&sck_cs_delay);
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|
|
chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
|
|
SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
|
|
|
|
chip->void_write_data = 0;
|
|
|
|
clkrate = clk_get_rate(dspi->clk);
|
|
hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
|
|
|
|
/* Set PCS to SCK delay scale values */
|
|
ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
|
|
|
|
/* Set After SCK delay scale values */
|
|
ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
|
|
|
|
chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
|
|
| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
|
|
| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
|
|
| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
|
|
| SPI_CTAR_PCSSCK(pcssck)
|
|
| SPI_CTAR_CSSCK(cssck)
|
|
| SPI_CTAR_PASC(pasc)
|
|
| SPI_CTAR_ASC(asc)
|
|
| SPI_CTAR_PBR(pbr)
|
|
| SPI_CTAR_BR(br);
|
|
|
|
spi_set_ctldata(spi, chip);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dspi_cleanup(struct spi_device *spi)
|
|
{
|
|
struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
|
|
|
|
dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
|
|
spi->master->bus_num, spi->chip_select);
|
|
|
|
kfree(chip);
|
|
}
|
|
|
|
static irqreturn_t dspi_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
|
|
struct spi_message *msg = dspi->cur_msg;
|
|
enum dspi_trans_mode trans_mode;
|
|
u32 spi_sr, spi_tcr;
|
|
u32 spi_tcnt, tcnt_diff;
|
|
int tx_word;
|
|
|
|
regmap_read(dspi->regmap, SPI_SR, &spi_sr);
|
|
regmap_write(dspi->regmap, SPI_SR, spi_sr);
|
|
|
|
|
|
if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
|
|
tx_word = is_double_byte_mode(dspi);
|
|
|
|
regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
|
|
spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
|
|
/*
|
|
* The width of SPI Transfer Counter in SPI_TCR is 16bits,
|
|
* so the max couner is 65535. When the counter reach 65535,
|
|
* it will wrap around, counter reset to zero.
|
|
* spi_tcnt my be less than dspi->spi_tcnt, it means the
|
|
* counter already wrapped around.
|
|
* SPI Transfer Counter is a counter of transmitted frames.
|
|
* The size of frame maybe two bytes.
|
|
*/
|
|
tcnt_diff = ((spi_tcnt + SPI_TCR_TCNT_MAX) - dspi->spi_tcnt)
|
|
% SPI_TCR_TCNT_MAX;
|
|
tcnt_diff *= (tx_word + 1);
|
|
if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
|
|
tcnt_diff--;
|
|
|
|
msg->actual_length += tcnt_diff;
|
|
|
|
dspi->spi_tcnt = spi_tcnt;
|
|
|
|
trans_mode = dspi->devtype_data->trans_mode;
|
|
switch (trans_mode) {
|
|
case DSPI_EOQ_MODE:
|
|
dspi_eoq_read(dspi);
|
|
break;
|
|
case DSPI_TCFQ_MODE:
|
|
dspi_tcfq_read(dspi);
|
|
break;
|
|
default:
|
|
dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
|
|
trans_mode);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
if (!dspi->len) {
|
|
if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) {
|
|
regmap_update_bits(dspi->regmap,
|
|
SPI_CTAR(0),
|
|
SPI_FRAME_BITS_MASK,
|
|
SPI_FRAME_BITS(16));
|
|
dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM;
|
|
}
|
|
|
|
dspi->waitflags = 1;
|
|
wake_up_interruptible(&dspi->waitq);
|
|
} else {
|
|
switch (trans_mode) {
|
|
case DSPI_EOQ_MODE:
|
|
dspi_eoq_write(dspi);
|
|
break;
|
|
case DSPI_TCFQ_MODE:
|
|
dspi_tcfq_write(dspi);
|
|
break;
|
|
default:
|
|
dev_err(&dspi->pdev->dev,
|
|
"unsupported trans_mode %u\n",
|
|
trans_mode);
|
|
}
|
|
}
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const struct of_device_id fsl_dspi_dt_ids[] = {
|
|
{ .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, },
|
|
{ .compatible = "fsl,ls1021a-v1.0-dspi",
|
|
.data = (void *)&ls1021a_v1_data, },
|
|
{ .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int dspi_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct fsl_dspi *dspi = spi_master_get_devdata(master);
|
|
|
|
spi_master_suspend(master);
|
|
clk_disable_unprepare(dspi->clk);
|
|
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dspi_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct fsl_dspi *dspi = spi_master_get_devdata(master);
|
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
clk_prepare_enable(dspi->clk);
|
|
spi_master_resume(master);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
|
|
|
|
static const struct regmap_config dspi_regmap_config = {
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
.reg_stride = 4,
|
|
.max_register = 0x88,
|
|
};
|
|
|
|
static int dspi_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct spi_master *master;
|
|
struct fsl_dspi *dspi;
|
|
struct resource *res;
|
|
void __iomem *base;
|
|
int ret = 0, cs_num, bus_num;
|
|
const struct of_device_id *of_id =
|
|
of_match_device(fsl_dspi_dt_ids, &pdev->dev);
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
dspi = spi_master_get_devdata(master);
|
|
dspi->pdev = pdev;
|
|
dspi->master = master;
|
|
|
|
master->transfer = NULL;
|
|
master->setup = dspi_setup;
|
|
master->transfer_one_message = dspi_transfer_one_message;
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
|
|
master->cleanup = dspi_cleanup;
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
|
master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
|
|
SPI_BPW_MASK(16);
|
|
|
|
ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
|
|
goto out_master_put;
|
|
}
|
|
master->num_chipselect = cs_num;
|
|
|
|
ret = of_property_read_u32(np, "bus-num", &bus_num);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "can't get bus-num\n");
|
|
goto out_master_put;
|
|
}
|
|
master->bus_num = bus_num;
|
|
|
|
dspi->devtype_data = (struct fsl_dspi_devtype_data *)of_id->data;
|
|
if (!dspi->devtype_data) {
|
|
dev_err(&pdev->dev, "can't get devtype_data\n");
|
|
ret = -EFAULT;
|
|
goto out_master_put;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(base)) {
|
|
ret = PTR_ERR(base);
|
|
goto out_master_put;
|
|
}
|
|
|
|
dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
|
|
&dspi_regmap_config);
|
|
if (IS_ERR(dspi->regmap)) {
|
|
dev_err(&pdev->dev, "failed to init regmap: %ld\n",
|
|
PTR_ERR(dspi->regmap));
|
|
return PTR_ERR(dspi->regmap);
|
|
}
|
|
|
|
dspi->irq = platform_get_irq(pdev, 0);
|
|
if (dspi->irq < 0) {
|
|
dev_err(&pdev->dev, "can't get platform irq\n");
|
|
ret = dspi->irq;
|
|
goto out_master_put;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
|
|
pdev->name, dspi);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
|
|
goto out_master_put;
|
|
}
|
|
|
|
dspi->clk = devm_clk_get(&pdev->dev, "dspi");
|
|
if (IS_ERR(dspi->clk)) {
|
|
ret = PTR_ERR(dspi->clk);
|
|
dev_err(&pdev->dev, "unable to get clock\n");
|
|
goto out_master_put;
|
|
}
|
|
clk_prepare_enable(dspi->clk);
|
|
|
|
master->max_speed_hz =
|
|
clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
|
|
|
|
init_waitqueue_head(&dspi->waitq);
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
ret = spi_register_master(master);
|
|
if (ret != 0) {
|
|
dev_err(&pdev->dev, "Problem registering DSPI master\n");
|
|
goto out_clk_put;
|
|
}
|
|
|
|
return ret;
|
|
|
|
out_clk_put:
|
|
clk_disable_unprepare(dspi->clk);
|
|
out_master_put:
|
|
spi_master_put(master);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct fsl_dspi *dspi = spi_master_get_devdata(master);
|
|
|
|
/* Disconnect from the SPI framework */
|
|
clk_disable_unprepare(dspi->clk);
|
|
spi_unregister_master(dspi->master);
|
|
spi_master_put(dspi->master);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver fsl_dspi_driver = {
|
|
.driver.name = DRIVER_NAME,
|
|
.driver.of_match_table = fsl_dspi_dt_ids,
|
|
.driver.owner = THIS_MODULE,
|
|
.driver.pm = &dspi_pm,
|
|
.probe = dspi_probe,
|
|
.remove = dspi_remove,
|
|
};
|
|
module_platform_driver(fsl_dspi_driver);
|
|
|
|
MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|