forked from Minki/linux
3b12308f33
Add basic support for Atheros AR5312/AR2312 SoCs: registers definition file and initial setup code. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8238/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
156 lines
4.4 KiB
C
156 lines
4.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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* Copyright (C) 2006 FON Technology, SL.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
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*/
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/*
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* Platform devices for Atheros AR5312 SoCs
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/reboot.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include "devices.h"
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#include "ar5312.h"
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#include "ar5312_regs.h"
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static void __iomem *ar5312_rst_base;
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static inline u32 ar5312_rst_reg_read(u32 reg)
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{
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return __raw_readl(ar5312_rst_base + reg);
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}
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static inline void ar5312_rst_reg_write(u32 reg, u32 val)
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{
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__raw_writel(val, ar5312_rst_base + reg);
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}
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static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
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{
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u32 ret = ar5312_rst_reg_read(reg);
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ret &= ~mask;
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ret |= val;
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ar5312_rst_reg_write(reg, ret);
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}
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static void ar5312_restart(char *command)
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{
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/* reset the system */
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local_irq_disable();
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while (1)
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ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
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}
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/*
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* This table is indexed by bits 5..4 of the CLOCKCTL1 register
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* to determine the predevisor value.
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*/
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static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
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static unsigned __init ar5312_cpu_frequency(void)
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{
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u32 scratch, devid, clock_ctl1;
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u32 predivide_mask, multiplier_mask, doubler_mask;
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unsigned predivide_shift, multiplier_shift;
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unsigned predivide_select, predivisor, multiplier;
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/* Trust the bootrom's idea of cpu frequency. */
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scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
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if (scratch)
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return scratch;
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devid = ar5312_rst_reg_read(AR5312_REV);
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devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
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if (devid == AR5312_REV_MAJ_AR2313) {
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predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
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predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
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multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
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multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
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doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
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} else { /* AR5312 and AR2312 */
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predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
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predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
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multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
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multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
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doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
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}
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/*
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* Clocking is derived from a fixed 40MHz input clock.
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*
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* cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
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* sys_freq = cpu_freq / 4 (used for APB clock, serial,
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* flash, Timer, Watchdog Timer)
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*
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* cnt_freq = cpu_freq / 2 (use for CPU count/compare)
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*
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* So, for example, with a PLL multiplier of 5, we have
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*
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* cpu_freq = 200MHz
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* sys_freq = 50MHz
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* cnt_freq = 100MHz
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*
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* We compute the CPU frequency, based on PLL settings.
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*/
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clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
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predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
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predivisor = clockctl1_predivide_table[predivide_select];
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multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
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if (clock_ctl1 & doubler_mask)
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multiplier <<= 1;
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return (40000000 / predivisor) * multiplier;
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}
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static inline unsigned ar5312_sys_frequency(void)
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{
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return ar5312_cpu_frequency() / 4;
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}
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void __init ar5312_plat_time_init(void)
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{
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mips_hpt_frequency = ar5312_cpu_frequency() / 2;
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}
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void __init ar5312_plat_mem_setup(void)
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{
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void __iomem *sdram_base;
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u32 memsize, memcfg, bank0_ac, bank1_ac;
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/* Detect memory size */
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sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
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AR5312_SDRAMCTL_SIZE);
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memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
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bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
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bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
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memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
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(bank1_ac ? (1 << (bank1_ac + 1)) : 0);
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memsize <<= 20;
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add_memory_region(0, memsize, BOOT_MEM_RAM);
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iounmap(sdram_base);
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ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
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/* Clear any lingering AHB errors */
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ar5312_rst_reg_read(AR5312_PROCADDR);
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ar5312_rst_reg_read(AR5312_DMAADDR);
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ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
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_machine_restart = ar5312_restart;
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}
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