781eef5b34
This improves performance by allowing the scheduler to move the tx scheduling work to idle CPUs. Since tx scheduling work is very latency sensitive and kept short via AQL, sched_set_fifo_low is used to keep worker priority above normal tasks Signed-off-by: Felix Fietkau <nbd@nbd.name>
320 lines
6.6 KiB
C
320 lines
6.6 KiB
C
// SPDX-License-Identifier: ISC
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/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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*/
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#include <linux/delay.h>
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#include "mt76x2.h"
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#include "eeprom.h"
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#include "mcu.h"
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#include "../mt76x02_mac.h"
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static void
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mt76x2_mac_pbf_init(struct mt76x02_dev *dev)
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{
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u32 val;
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val = MT_PBF_SYS_CTRL_MCU_RESET |
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MT_PBF_SYS_CTRL_DMA_RESET |
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MT_PBF_SYS_CTRL_MAC_RESET |
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MT_PBF_SYS_CTRL_PBF_RESET |
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MT_PBF_SYS_CTRL_ASY_RESET;
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mt76_set(dev, MT_PBF_SYS_CTRL, val);
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mt76_clear(dev, MT_PBF_SYS_CTRL, val);
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mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
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mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
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}
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static void
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mt76x2_fixup_xtal(struct mt76x02_dev *dev)
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{
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u16 eep_val;
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s8 offset = 0;
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eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
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offset = eep_val & 0x7f;
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if ((eep_val & 0xff) == 0xff)
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offset = 0;
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else if (eep_val & 0x80)
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offset = 0 - offset;
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eep_val >>= 8;
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if (eep_val == 0x00 || eep_val == 0xff) {
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eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
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eep_val &= 0xff;
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if (eep_val == 0x00 || eep_val == 0xff)
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eep_val = 0x14;
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}
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eep_val &= 0x7f;
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mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
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mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
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eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
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switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
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case 0:
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mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
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break;
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case 1:
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mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
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break;
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default:
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break;
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}
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}
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int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard)
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{
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const u8 *macaddr = dev->mt76.macaddr;
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u32 val;
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int i, k;
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if (!mt76x02_wait_for_mac(&dev->mt76))
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return -ETIMEDOUT;
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val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
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val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
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MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
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MT_WPDMA_GLO_CFG_RX_DMA_EN |
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MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
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MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
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val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
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mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
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mt76x2_mac_pbf_init(dev);
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mt76_write_mac_initvals(dev);
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mt76x2_fixup_xtal(dev);
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mt76_clear(dev, MT_MAC_SYS_CTRL,
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MT_MAC_SYS_CTRL_RESET_CSR |
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MT_MAC_SYS_CTRL_RESET_BBP);
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if (is_mt7612(dev))
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mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
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mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
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mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
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mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
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mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
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usleep_range(5000, 10000);
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mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
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mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
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mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
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mt76x02_mac_setaddr(dev, macaddr);
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mt76x02e_init_beacon_config(dev);
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if (!hard)
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return 0;
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for (i = 0; i < 256 / 32; i++)
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mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);
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for (i = 0; i < 256; i++) {
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mt76x02_mac_wcid_setup(dev, i, 0, NULL);
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mt76_wr(dev, MT_WCID_TX_RATE(i), 0);
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mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0);
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}
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for (i = 0; i < MT_MAX_VIFS; i++)
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mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL);
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for (i = 0; i < 16; i++)
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for (k = 0; k < 4; k++)
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mt76x02_mac_shared_key_setup(dev, i, k, NULL);
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for (i = 0; i < 16; i++)
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mt76_rr(dev, MT_TX_STAT_FIFO);
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mt76x02_set_tx_ackto(dev);
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return 0;
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}
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static void
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mt76x2_power_on_rf_patch(struct mt76x02_dev *dev)
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{
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mt76_set(dev, 0x10130, BIT(0) | BIT(16));
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udelay(1);
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mt76_clear(dev, 0x1001c, 0xff);
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mt76_set(dev, 0x1001c, 0x30);
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mt76_wr(dev, 0x10014, 0x484f);
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udelay(1);
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mt76_set(dev, 0x10130, BIT(17));
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udelay(125);
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mt76_clear(dev, 0x10130, BIT(16));
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udelay(50);
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mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
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}
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static void
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mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit)
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{
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int shift = unit ? 8 : 0;
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/* Enable RF BG */
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mt76_set(dev, 0x10130, BIT(0) << shift);
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udelay(10);
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/* Enable RFDIG LDO/AFE/ABB/ADDA */
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mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
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udelay(10);
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/* Switch RFDIG power to internal LDO */
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mt76_clear(dev, 0x10130, BIT(2) << shift);
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udelay(10);
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mt76x2_power_on_rf_patch(dev);
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mt76_set(dev, 0x530, 0xf);
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}
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static void
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mt76x2_power_on(struct mt76x02_dev *dev)
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{
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u32 val;
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/* Turn on WL MTCMOS */
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mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
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val = MT_WLAN_MTC_CTRL_STATE_UP |
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MT_WLAN_MTC_CTRL_PWR_ACK |
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MT_WLAN_MTC_CTRL_PWR_ACK_S;
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mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
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mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
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udelay(10);
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mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
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udelay(10);
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mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
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mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
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/* Turn on AD/DA power down */
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mt76_clear(dev, 0x11204, BIT(3));
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/* WLAN function enable */
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mt76_set(dev, 0x10080, BIT(0));
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/* Release BBP software reset */
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mt76_clear(dev, 0x10064, BIT(18));
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mt76x2_power_on_rf(dev, 0);
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mt76x2_power_on_rf(dev, 1);
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}
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int mt76x2_resume_device(struct mt76x02_dev *dev)
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{
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int err;
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mt76x02_dma_disable(dev);
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mt76x2_reset_wlan(dev, true);
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mt76x2_power_on(dev);
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err = mt76x2_mac_reset(dev, true);
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if (err)
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return err;
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mt76x02_mac_start(dev);
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return mt76x2_mcu_init(dev);
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}
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static int mt76x2_init_hardware(struct mt76x02_dev *dev)
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{
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int ret;
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mt76x02_dma_disable(dev);
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mt76x2_reset_wlan(dev, true);
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mt76x2_power_on(dev);
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ret = mt76x2_eeprom_init(dev);
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if (ret)
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return ret;
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ret = mt76x2_mac_reset(dev, true);
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if (ret)
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return ret;
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dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
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ret = mt76x02_dma_init(dev);
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if (ret)
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return ret;
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set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
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mt76x02_mac_start(dev);
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ret = mt76x2_mcu_init(dev);
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if (ret)
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return ret;
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mt76x2_mac_stop(dev, false);
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return 0;
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}
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void mt76x2_stop_hardware(struct mt76x02_dev *dev)
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{
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cancel_delayed_work_sync(&dev->cal_work);
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cancel_delayed_work_sync(&dev->mt76.mac_work);
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cancel_delayed_work_sync(&dev->wdt_work);
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clear_bit(MT76_RESTART, &dev->mphy.state);
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mt76x02_mcu_set_radio_state(dev, false);
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mt76x2_mac_stop(dev, false);
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}
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void mt76x2_cleanup(struct mt76x02_dev *dev)
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{
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tasklet_disable(&dev->dfs_pd.dfs_tasklet);
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tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
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mt76x2_stop_hardware(dev);
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mt76_dma_cleanup(&dev->mt76);
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mt76x02_mcu_cleanup(dev);
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}
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int mt76x2_register_device(struct mt76x02_dev *dev)
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{
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int ret;
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INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate);
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mt76x02_init_device(dev);
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ret = mt76x2_init_hardware(dev);
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if (ret)
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return ret;
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mt76x02_config_mac_addr_list(dev);
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ret = mt76_register_device(&dev->mt76, true, mt76x02_rates,
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ARRAY_SIZE(mt76x02_rates));
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if (ret)
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goto fail;
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mt76x02_init_debugfs(dev);
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mt76x2_init_txpower(dev, &dev->mphy.sband_2g.sband);
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mt76x2_init_txpower(dev, &dev->mphy.sband_5g.sband);
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return 0;
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fail:
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mt76x2_stop_hardware(dev);
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return ret;
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}
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