linux/arch/powerpc/include/asm/nohash/32
Christophe Leroy 33fe43cfd9 powerpc/8xx: Manage _PAGE_ACCESSED through APG bits in L1 entry
When _PAGE_ACCESSED is not set, a minor fault is expected.
To do this, TLB miss exception ANDs _PAGE_PRESENT and _PAGE_ACCESSED
into the L2 entry valid bit.

To simplify the processing and reduce the number of instructions in
TLB miss exceptions, manage it as an APG bit and get it next to
_PAGE_GUARDED bit to allow a copy in one go. Then declare the
corresponding groups as handling all accesses as user accesses.
As the PP bits always define user as No Access, it will generate
a fault.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/80f488db230c6b0e7b3b990d72bd94a8a069e93e.1602492856.git.christophe.leroy@csgroup.eu
2020-11-05 23:34:25 +11:00
..
hugetlb-8xx.h powerpc/8xx: Support 16k hugepages with 4k pages 2020-09-15 22:13:31 +10:00
kup-8xx.h powerpc/8xx: Manage _PAGE_ACCESSED through APG bits in L1 entry 2020-11-05 23:34:25 +11:00
mmu-8xx.h powerpc/8xx: Manage _PAGE_ACCESSED through APG bits in L1 entry 2020-11-05 23:34:25 +11:00
mmu-40x.h powerpc/mm: move platform specific mmu-xxx.h in platform directories 2018-12-04 19:45:01 +11:00
mmu-44x.h powerpc/44x: use patch_sites for TLB handlers patching 2018-12-19 18:56:32 +11:00
pgalloc.h powerpc/mm: refactor pgd_alloc() and pgd_free() on nohash 2019-05-03 01:20:25 +10:00
pgtable.h powerpc/8xx: Support 16k hugepages with 4k pages 2020-09-15 22:13:31 +10:00
pte-8xx.h powerpc/8xx: Manage _PAGE_ACCESSED through APG bits in L1 entry 2020-11-05 23:34:25 +11:00
pte-40x.h powerpc/40x: Rework 40x PTE access and TLB miss 2020-05-28 23:24:34 +10:00
pte-44x.h powerpc/mm: Make pte_pgprot return all pte bits 2018-10-19 00:56:17 +11:00
pte-fsl-booke.h powerpc/mm: Make pte_pgprot return all pte bits 2018-10-19 00:56:17 +11:00