2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
98 lines
2.8 KiB
C
98 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* include/asm-mips/vr41xx/irq.h
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*
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* Interrupt numbers for NEC VR4100 series.
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*
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* Copyright (C) 1999 Michael Klar
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* Copyright (C) 2001, 2002 Paul Mundt
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* Copyright (C) 2002 MontaVista Software, Inc.
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* Copyright (C) 2002 TimeSys Corp.
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* Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
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*/
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#ifndef __NEC_VR41XX_IRQ_H
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#define __NEC_VR41XX_IRQ_H
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/*
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* CPU core Interrupt Numbers
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*/
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#define MIPS_CPU_IRQ_BASE 0
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#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
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#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
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#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
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#define INT0_IRQ MIPS_CPU_IRQ(2)
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#define INT1_IRQ MIPS_CPU_IRQ(3)
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#define INT2_IRQ MIPS_CPU_IRQ(4)
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#define INT3_IRQ MIPS_CPU_IRQ(5)
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#define INT4_IRQ MIPS_CPU_IRQ(6)
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#define TIMER_IRQ MIPS_CPU_IRQ(7)
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/*
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* SYINT1 Interrupt Numbers
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*/
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#define SYSINT1_IRQ_BASE 8
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#define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x))
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#define BATTRY_IRQ SYSINT1_IRQ(0)
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#define POWER_IRQ SYSINT1_IRQ(1)
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#define RTCLONG1_IRQ SYSINT1_IRQ(2)
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#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3)
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/* RFU */
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#define PIU_IRQ SYSINT1_IRQ(5)
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#define AIU_IRQ SYSINT1_IRQ(6)
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#define KIU_IRQ SYSINT1_IRQ(7)
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#define GIUINT_IRQ SYSINT1_IRQ(8)
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#define SIU_IRQ SYSINT1_IRQ(9)
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#define BUSERR_IRQ SYSINT1_IRQ(10)
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#define SOFTINT_IRQ SYSINT1_IRQ(11)
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#define CLKRUN_IRQ SYSINT1_IRQ(12)
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#define DOZEPIU_IRQ SYSINT1_IRQ(13)
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#define SYSINT1_IRQ_LAST DOZEPIU_IRQ
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/*
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* SYSINT2 Interrupt Numbers
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*/
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#define SYSINT2_IRQ_BASE 24
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#define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x))
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#define RTCLONG2_IRQ SYSINT2_IRQ(0)
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#define LED_IRQ SYSINT2_IRQ(1)
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#define HSP_IRQ SYSINT2_IRQ(2)
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#define TCLOCK_IRQ SYSINT2_IRQ(3)
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#define FIR_IRQ SYSINT2_IRQ(4)
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#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */
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#define DSIU_IRQ SYSINT2_IRQ(5)
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#define PCI_IRQ SYSINT2_IRQ(6)
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#define SCU_IRQ SYSINT2_IRQ(7)
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#define CSI_IRQ SYSINT2_IRQ(8)
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#define BCU_IRQ SYSINT2_IRQ(9)
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#define ETHERNET_IRQ SYSINT2_IRQ(10)
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#define SYSINT2_IRQ_LAST ETHERNET_IRQ
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/*
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* GIU Interrupt Numbers
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*/
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#define GIU_IRQ_BASE 40
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#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
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#define GIU_IRQ_LAST GIU_IRQ(31)
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/*
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* VRC4173 Interrupt Numbers
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*/
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#define VRC4173_IRQ_BASE 72
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#define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x))
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#define VRC4173_USB_IRQ VRC4173_IRQ(0)
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#define VRC4173_PCMCIA2_IRQ VRC4173_IRQ(1)
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#define VRC4173_PCMCIA1_IRQ VRC4173_IRQ(2)
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#define VRC4173_PS2CH2_IRQ VRC4173_IRQ(3)
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#define VRC4173_PS2CH1_IRQ VRC4173_IRQ(4)
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#define VRC4173_PIU_IRQ VRC4173_IRQ(5)
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#define VRC4173_AIU_IRQ VRC4173_IRQ(6)
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#define VRC4173_KIU_IRQ VRC4173_IRQ(7)
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#define VRC4173_GIU_IRQ VRC4173_IRQ(8)
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#define VRC4173_AC97_IRQ VRC4173_IRQ(9)
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#define VRC4173_AC97INT1_IRQ VRC4173_IRQ(10)
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/* RFU */
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#define VRC4173_DOZEPIU_IRQ VRC4173_IRQ(13)
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#define VRC4173_IRQ_LAST VRC4173_DOZEPIU_IRQ
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#endif /* __NEC_VR41XX_IRQ_H */
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