bfaf245022
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for Linux 4.1. Most
noteworthy:
- Add more Octeon-optimized crypto functions
- Octeon crypto preemption and locking fixes
- Little endian support for Octeon
- Use correct CSR to soft reset Octeons
- Support LEDs on the Octeon-based DSR-1000N
- Fix PCI interrupt mapping for the Octeon-based DSR-1000N
- Mark prom_free_prom_memory() as __init for a number of systems
- Support for Imagination's Pistachio SOC. This includes arch and
CLK bits. I'd like to merge pinctrl bits later
- Improve parallelism of csum_partial for certain pipelines
- Organize DTB files in subdirs like other architectures
- Implement read_sched_clock for all MIPS platforms other than
Octeon
- Massive series of 38 fixes and cleanups for the FPU emulator /
kernel
- Further FPU remulator work to support new features. This sits on a
separate branch which also has been pulled into the 4.1 KVM branch
- Clean up and fixes for the SEAD3 eval board; remove unused file
- Various updates for Netlogic platforms
- A number of small updates for Loongson 3 platforms
- Increase the memory limit for ATH79 platforms to 256MB
- A fair number of fixes and updates for BCM47xx platforms
- Finish the implementation of XPA support
- MIPS FDC support. No, not floppy controller but Fast Debug Channel :)
- Detect the R16000 used in SGI legacy platforms
- Fix Kconfig dependencies for the SSB bus support"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits)
MIPS: Makefile: Fix MIPS ASE detection code
MIPS: asm: elf: Set O32 default FPU flags
MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
MIPS: Kconfig: Disable SMP/CPS for 64-bit
MIPS: Hibernate: flush TLB entries earlier
MIPS: smp-cps: cpu_set FPU mask if FPU present
MIPS: lose_fpu(): Disable FPU when MSA enabled
MIPS: ralink: add missing symbol for RALINK_ILL_ACC
MIPS: ralink: Fix bad config symbol in PCI makefile.
SSB: fix Kconfig dependencies
MIPS: Malta: Detect and fix bad memsize values
Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
MIPS: Fix cpu_has_mips_r2_exec_hazard.
MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
MIPS: unaligned: Fix regular load/store instruction emulation for EVA
MIPS: unaligned: Surround load/store macros in do {} while statements
...
225 lines
4.4 KiB
C
225 lines
4.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012-2013 Cavium Inc., All Rights Reserved.
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*
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* MD5/SHA1/SHA256/SHA512 instruction definitions added by
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* Aaro Koskinen <aaro.koskinen@iki.fi>.
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*
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*/
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#ifndef __LINUX_OCTEON_CRYPTO_H
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#define __LINUX_OCTEON_CRYPTO_H
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#include <linux/sched.h>
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#include <asm/mipsregs.h>
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#define OCTEON_CR_OPCODE_PRIORITY 300
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extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
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extern void octeon_crypto_disable(struct octeon_cop2_state *state,
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unsigned long flags);
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/*
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* Macros needed to implement MD5/SHA1/SHA256:
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*/
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/*
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* The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
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*/
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#define write_octeon_64bit_hash_dword(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0048+" STR(index) \
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: \
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: [rt] "d" (cpu_to_be64(value))); \
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} while (0)
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/*
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* The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
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*/
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#define read_octeon_64bit_hash_dword(index) \
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({ \
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u64 __value; \
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\
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__asm__ __volatile__ ( \
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"dmfc2 %[rt],0x0048+" STR(index) \
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: [rt] "=d" (__value) \
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: ); \
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\
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be64_to_cpu(__value); \
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})
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/*
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* The index can be 0-6.
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*/
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#define write_octeon_64bit_block_dword(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0040+" STR(index) \
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: \
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: [rt] "d" (cpu_to_be64(value))); \
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} while (0)
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/*
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* The value is the final block dword (64-bit).
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*/
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#define octeon_md5_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x4047" \
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: \
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: [rt] "d" (cpu_to_be64(value))); \
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} while (0)
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/*
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* The value is the final block dword (64-bit).
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*/
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#define octeon_sha1_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x4057" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The value is the final block dword (64-bit).
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*/
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#define octeon_sha256_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x404f" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* Macros needed to implement SHA512:
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*/
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/*
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* The index can be 0-7.
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*/
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#define write_octeon_64bit_hash_sha512(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0250+" STR(index) \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The index can be 0-7.
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*/
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#define read_octeon_64bit_hash_sha512(index) \
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({ \
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u64 __value; \
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\
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__asm__ __volatile__ ( \
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"dmfc2 %[rt],0x0250+" STR(index) \
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: [rt] "=d" (__value) \
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: ); \
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\
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__value; \
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})
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/*
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* The index can be 0-14.
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*/
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#define write_octeon_64bit_block_sha512(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0240+" STR(index) \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The value is the final block word (64-bit).
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*/
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#define octeon_sha512_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x424f" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The value is the final block dword (64-bit).
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*/
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#define octeon_sha1_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x4057" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The value is the final block dword (64-bit).
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*/
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#define octeon_sha256_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x404f" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* Macros needed to implement SHA512:
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*/
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/*
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* The index can be 0-7.
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*/
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#define write_octeon_64bit_hash_sha512(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0250+" STR(index) \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The index can be 0-7.
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*/
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#define read_octeon_64bit_hash_sha512(index) \
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({ \
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u64 __value; \
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\
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__asm__ __volatile__ ( \
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"dmfc2 %[rt],0x0250+" STR(index) \
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: [rt] "=d" (__value) \
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: ); \
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\
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__value; \
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})
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/*
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* The index can be 0-14.
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*/
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#define write_octeon_64bit_block_sha512(value, index) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x0240+" STR(index) \
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: \
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: [rt] "d" (value)); \
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} while (0)
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/*
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* The value is the final block word (64-bit).
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*/
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#define octeon_sha512_start(value) \
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do { \
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__asm__ __volatile__ ( \
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"dmtc2 %[rt],0x424f" \
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: \
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: [rt] "d" (value)); \
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} while (0)
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#endif /* __LINUX_OCTEON_CRYPTO_H */
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