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linux/arch/csky/abiv1
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Guo Ren 0c8a32eed1 csky: Add memory layout 2.5G(user):1.5G(kernel) 
There are two ways for translating va to pa for csky:
 - Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk)
 - Use SSEG0/1 (Simple Segment Mapping)

We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1
are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0
to use 2G-2.5G as TLB user mapping.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2021-01-12 09:52:40 +08:00
..
inc/abi csky: Add memory layout 2.5G(user):1.5G(kernel) 2021-01-12 09:52:40 +08:00
alignment.c csky: Support kernel non-aligned access 2019-08-20 20:15:44 +08:00
bswapdi.c csky: Library functions 2018-10-26 00:54:24 +08:00
bswapsi.c csky: Library functions 2018-10-26 00:54:24 +08:00
cacheflush.c csky: Fixup 610 vipt cache flush mechanism 2019-08-22 10:44:24 +08:00
Makefile csky: Fixup abiv1 memset error 2019-07-19 14:21:36 +08:00
memcpy.S csky: Library functions 2018-10-26 00:54:24 +08:00
mmap.c csky: Fixup arch_get_unmapped_area() implementation 2019-08-20 16:09:37 +08:00
strksyms.c csky: Fixup abiv1 memset error 2019-07-19 14:21:36 +08:00