forked from Minki/linux
f54d186700
I plan to usurp the short name of struct fence for a core kernel struct, and so I need to rename the specialised fence/timeline for DMA operations to make room. A consensus was reached in https://lists.freedesktop.org/archives/dri-devel/2016-July/113083.html that making clear this fence applies to DMA operations was a good thing. Since then the patch has grown a bit as usage increases, so hopefully it remains a good thing! (v2...: rebase, rerun spatch) v3: Compile on msm, spotted a manual fixup that I broke. v4: Try again for msm, sorry Daniel coccinelle script: @@ @@ - struct fence + struct dma_fence @@ @@ - struct fence_ops + struct dma_fence_ops @@ @@ - struct fence_cb + struct dma_fence_cb @@ @@ - struct fence_array + struct dma_fence_array @@ @@ - enum fence_flag_bits + enum dma_fence_flag_bits @@ @@ ( - fence_init + dma_fence_init | - fence_release + dma_fence_release | - fence_free + dma_fence_free | - fence_get + dma_fence_get | - fence_get_rcu + dma_fence_get_rcu | - fence_put + dma_fence_put | - fence_signal + dma_fence_signal | - fence_signal_locked + dma_fence_signal_locked | - fence_default_wait + dma_fence_default_wait | - fence_add_callback + dma_fence_add_callback | - fence_remove_callback + dma_fence_remove_callback | - fence_enable_sw_signaling + dma_fence_enable_sw_signaling | - fence_is_signaled_locked + dma_fence_is_signaled_locked | - fence_is_signaled + dma_fence_is_signaled | - fence_is_later + dma_fence_is_later | - fence_later + dma_fence_later | - fence_wait_timeout + dma_fence_wait_timeout | - fence_wait_any_timeout + dma_fence_wait_any_timeout | - fence_wait + dma_fence_wait | - fence_context_alloc + dma_fence_context_alloc | - fence_array_create + dma_fence_array_create | - to_fence_array + to_dma_fence_array | - fence_is_array + dma_fence_is_array | - trace_fence_emit + trace_dma_fence_emit | - FENCE_TRACE + DMA_FENCE_TRACE | - FENCE_WARN + DMA_FENCE_WARN | - FENCE_ERR + DMA_FENCE_ERR ) ( ... ) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Acked-by: Sumit Semwal <sumit.semwal@linaro.org> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161025120045.28839-1-chris@chris-wilson.co.uk
714 lines
16 KiB
C
714 lines
16 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "msm_gpu.h"
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#include "msm_gem.h"
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#include "msm_mmu.h"
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#include "msm_fence.h"
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/*
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* Power Management:
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*/
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#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
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#include <mach/board.h>
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static void bs_init(struct msm_gpu *gpu)
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{
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if (gpu->bus_scale_table) {
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gpu->bsc = msm_bus_scale_register_client(gpu->bus_scale_table);
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DBG("bus scale client: %08x", gpu->bsc);
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}
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}
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static void bs_fini(struct msm_gpu *gpu)
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{
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if (gpu->bsc) {
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msm_bus_scale_unregister_client(gpu->bsc);
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gpu->bsc = 0;
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}
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}
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static void bs_set(struct msm_gpu *gpu, int idx)
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{
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if (gpu->bsc) {
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DBG("set bus scaling: %d", idx);
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msm_bus_scale_client_update_request(gpu->bsc, idx);
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}
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}
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#else
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static void bs_init(struct msm_gpu *gpu) {}
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static void bs_fini(struct msm_gpu *gpu) {}
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static void bs_set(struct msm_gpu *gpu, int idx) {}
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#endif
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static int enable_pwrrail(struct msm_gpu *gpu)
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{
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struct drm_device *dev = gpu->dev;
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int ret = 0;
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if (gpu->gpu_reg) {
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ret = regulator_enable(gpu->gpu_reg);
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if (ret) {
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dev_err(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
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return ret;
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}
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}
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if (gpu->gpu_cx) {
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ret = regulator_enable(gpu->gpu_cx);
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if (ret) {
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dev_err(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
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return ret;
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}
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}
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return 0;
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}
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static int disable_pwrrail(struct msm_gpu *gpu)
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{
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if (gpu->gpu_cx)
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regulator_disable(gpu->gpu_cx);
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if (gpu->gpu_reg)
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regulator_disable(gpu->gpu_reg);
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return 0;
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}
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static int enable_clk(struct msm_gpu *gpu)
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{
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struct clk *rate_clk = NULL;
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int i;
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/* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */
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for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) {
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if (gpu->grp_clks[i]) {
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clk_prepare(gpu->grp_clks[i]);
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rate_clk = gpu->grp_clks[i];
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}
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}
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if (rate_clk && gpu->fast_rate)
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clk_set_rate(rate_clk, gpu->fast_rate);
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for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--)
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if (gpu->grp_clks[i])
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clk_enable(gpu->grp_clks[i]);
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return 0;
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}
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static int disable_clk(struct msm_gpu *gpu)
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{
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struct clk *rate_clk = NULL;
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int i;
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/* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */
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for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) {
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if (gpu->grp_clks[i]) {
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clk_disable(gpu->grp_clks[i]);
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rate_clk = gpu->grp_clks[i];
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}
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}
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if (rate_clk && gpu->slow_rate)
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clk_set_rate(rate_clk, gpu->slow_rate);
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for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--)
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if (gpu->grp_clks[i])
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clk_unprepare(gpu->grp_clks[i]);
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return 0;
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}
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static int enable_axi(struct msm_gpu *gpu)
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{
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if (gpu->ebi1_clk)
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clk_prepare_enable(gpu->ebi1_clk);
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if (gpu->bus_freq)
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bs_set(gpu, gpu->bus_freq);
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return 0;
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}
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static int disable_axi(struct msm_gpu *gpu)
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{
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if (gpu->ebi1_clk)
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clk_disable_unprepare(gpu->ebi1_clk);
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if (gpu->bus_freq)
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bs_set(gpu, 0);
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return 0;
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}
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int msm_gpu_pm_resume(struct msm_gpu *gpu)
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{
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struct drm_device *dev = gpu->dev;
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int ret;
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DBG("%s: active_cnt=%d", gpu->name, gpu->active_cnt);
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WARN_ON(!mutex_is_locked(&dev->struct_mutex));
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if (gpu->active_cnt++ > 0)
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return 0;
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if (WARN_ON(gpu->active_cnt <= 0))
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return -EINVAL;
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ret = enable_pwrrail(gpu);
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if (ret)
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return ret;
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ret = enable_clk(gpu);
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if (ret)
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return ret;
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ret = enable_axi(gpu);
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if (ret)
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return ret;
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return 0;
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}
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int msm_gpu_pm_suspend(struct msm_gpu *gpu)
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{
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struct drm_device *dev = gpu->dev;
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int ret;
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DBG("%s: active_cnt=%d", gpu->name, gpu->active_cnt);
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WARN_ON(!mutex_is_locked(&dev->struct_mutex));
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if (--gpu->active_cnt > 0)
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return 0;
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if (WARN_ON(gpu->active_cnt < 0))
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return -EINVAL;
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ret = disable_axi(gpu);
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if (ret)
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return ret;
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ret = disable_clk(gpu);
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if (ret)
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return ret;
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ret = disable_pwrrail(gpu);
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if (ret)
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return ret;
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return 0;
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}
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/*
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* Inactivity detection (for suspend):
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*/
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static void inactive_worker(struct work_struct *work)
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{
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struct msm_gpu *gpu = container_of(work, struct msm_gpu, inactive_work);
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struct drm_device *dev = gpu->dev;
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if (gpu->inactive)
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return;
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DBG("%s: inactive!\n", gpu->name);
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mutex_lock(&dev->struct_mutex);
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if (!(msm_gpu_active(gpu) || gpu->inactive)) {
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disable_axi(gpu);
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disable_clk(gpu);
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gpu->inactive = true;
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}
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mutex_unlock(&dev->struct_mutex);
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}
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static void inactive_handler(unsigned long data)
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{
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struct msm_gpu *gpu = (struct msm_gpu *)data;
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struct msm_drm_private *priv = gpu->dev->dev_private;
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queue_work(priv->wq, &gpu->inactive_work);
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}
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/* cancel inactive timer and make sure we are awake: */
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static void inactive_cancel(struct msm_gpu *gpu)
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{
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DBG("%s", gpu->name);
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del_timer(&gpu->inactive_timer);
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if (gpu->inactive) {
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enable_clk(gpu);
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enable_axi(gpu);
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gpu->inactive = false;
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}
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}
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static void inactive_start(struct msm_gpu *gpu)
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{
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DBG("%s", gpu->name);
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mod_timer(&gpu->inactive_timer,
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round_jiffies_up(jiffies + DRM_MSM_INACTIVE_JIFFIES));
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}
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/*
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* Hangcheck detection for locked gpu:
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*/
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static void retire_submits(struct msm_gpu *gpu);
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static void recover_worker(struct work_struct *work)
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{
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struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
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struct drm_device *dev = gpu->dev;
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struct msm_gem_submit *submit;
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uint32_t fence = gpu->funcs->last_fence(gpu);
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msm_update_fence(gpu->fctx, fence + 1);
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mutex_lock(&dev->struct_mutex);
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dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name);
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list_for_each_entry(submit, &gpu->submit_list, node) {
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if (submit->fence->seqno == (fence + 1)) {
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struct task_struct *task;
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rcu_read_lock();
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task = pid_task(submit->pid, PIDTYPE_PID);
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if (task) {
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dev_err(dev->dev, "%s: offending task: %s\n",
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gpu->name, task->comm);
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}
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rcu_read_unlock();
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break;
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}
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}
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if (msm_gpu_active(gpu)) {
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/* retire completed submits, plus the one that hung: */
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retire_submits(gpu);
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inactive_cancel(gpu);
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gpu->funcs->recover(gpu);
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/* replay the remaining submits after the one that hung: */
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list_for_each_entry(submit, &gpu->submit_list, node) {
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gpu->funcs->submit(gpu, submit, NULL);
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}
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}
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mutex_unlock(&dev->struct_mutex);
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msm_gpu_retire(gpu);
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}
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static void hangcheck_timer_reset(struct msm_gpu *gpu)
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{
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DBG("%s", gpu->name);
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mod_timer(&gpu->hangcheck_timer,
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round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
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}
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static void hangcheck_handler(unsigned long data)
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{
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struct msm_gpu *gpu = (struct msm_gpu *)data;
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struct drm_device *dev = gpu->dev;
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struct msm_drm_private *priv = dev->dev_private;
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uint32_t fence = gpu->funcs->last_fence(gpu);
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if (fence != gpu->hangcheck_fence) {
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/* some progress has been made.. ya! */
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gpu->hangcheck_fence = fence;
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} else if (fence < gpu->fctx->last_fence) {
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/* no progress and not done.. hung! */
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gpu->hangcheck_fence = fence;
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dev_err(dev->dev, "%s: hangcheck detected gpu lockup!\n",
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gpu->name);
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dev_err(dev->dev, "%s: completed fence: %u\n",
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gpu->name, fence);
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dev_err(dev->dev, "%s: submitted fence: %u\n",
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gpu->name, gpu->fctx->last_fence);
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queue_work(priv->wq, &gpu->recover_work);
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}
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/* if still more pending work, reset the hangcheck timer: */
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if (gpu->fctx->last_fence > gpu->hangcheck_fence)
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hangcheck_timer_reset(gpu);
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/* workaround for missing irq: */
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queue_work(priv->wq, &gpu->retire_work);
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}
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/*
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* Performance Counters:
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*/
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/* called under perf_lock */
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static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
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{
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uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
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int i, n = min(ncntrs, gpu->num_perfcntrs);
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/* read current values: */
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for (i = 0; i < gpu->num_perfcntrs; i++)
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current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
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/* update cntrs: */
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for (i = 0; i < n; i++)
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cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
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/* save current values: */
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for (i = 0; i < gpu->num_perfcntrs; i++)
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gpu->last_cntrs[i] = current_cntrs[i];
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return n;
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}
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static void update_sw_cntrs(struct msm_gpu *gpu)
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{
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ktime_t time;
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uint32_t elapsed;
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unsigned long flags;
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spin_lock_irqsave(&gpu->perf_lock, flags);
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if (!gpu->perfcntr_active)
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goto out;
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time = ktime_get();
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elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
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gpu->totaltime += elapsed;
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if (gpu->last_sample.active)
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gpu->activetime += elapsed;
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gpu->last_sample.active = msm_gpu_active(gpu);
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gpu->last_sample.time = time;
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out:
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spin_unlock_irqrestore(&gpu->perf_lock, flags);
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}
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void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
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{
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unsigned long flags;
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spin_lock_irqsave(&gpu->perf_lock, flags);
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/* we could dynamically enable/disable perfcntr registers too.. */
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gpu->last_sample.active = msm_gpu_active(gpu);
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gpu->last_sample.time = ktime_get();
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gpu->activetime = gpu->totaltime = 0;
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gpu->perfcntr_active = true;
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update_hw_cntrs(gpu, 0, NULL);
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spin_unlock_irqrestore(&gpu->perf_lock, flags);
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}
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void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
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{
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gpu->perfcntr_active = false;
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}
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/* returns -errno or # of cntrs sampled */
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int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
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uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&gpu->perf_lock, flags);
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if (!gpu->perfcntr_active) {
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ret = -EINVAL;
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goto out;
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}
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*activetime = gpu->activetime;
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*totaltime = gpu->totaltime;
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gpu->activetime = gpu->totaltime = 0;
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ret = update_hw_cntrs(gpu, ncntrs, cntrs);
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out:
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spin_unlock_irqrestore(&gpu->perf_lock, flags);
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return ret;
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}
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/*
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* Cmdstream submission/retirement:
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*/
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static void retire_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
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{
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int i;
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for (i = 0; i < submit->nr_bos; i++) {
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struct msm_gem_object *msm_obj = submit->bos[i].obj;
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/* move to inactive: */
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msm_gem_move_to_inactive(&msm_obj->base);
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msm_gem_put_iova(&msm_obj->base, gpu->id);
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drm_gem_object_unreference(&msm_obj->base);
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}
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msm_gem_submit_free(submit);
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}
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static void retire_submits(struct msm_gpu *gpu)
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{
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struct drm_device *dev = gpu->dev;
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WARN_ON(!mutex_is_locked(&dev->struct_mutex));
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while (!list_empty(&gpu->submit_list)) {
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struct msm_gem_submit *submit;
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submit = list_first_entry(&gpu->submit_list,
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struct msm_gem_submit, node);
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if (dma_fence_is_signaled(submit->fence)) {
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retire_submit(gpu, submit);
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void retire_worker(struct work_struct *work)
|
|
{
|
|
struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
|
|
struct drm_device *dev = gpu->dev;
|
|
uint32_t fence = gpu->funcs->last_fence(gpu);
|
|
|
|
msm_update_fence(gpu->fctx, fence);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
retire_submits(gpu);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
if (!msm_gpu_active(gpu))
|
|
inactive_start(gpu);
|
|
}
|
|
|
|
/* call from irq handler to schedule work to retire bo's */
|
|
void msm_gpu_retire(struct msm_gpu *gpu)
|
|
{
|
|
struct msm_drm_private *priv = gpu->dev->dev_private;
|
|
queue_work(priv->wq, &gpu->retire_work);
|
|
update_sw_cntrs(gpu);
|
|
}
|
|
|
|
/* add bo's to gpu's ring, and kick gpu: */
|
|
void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
|
|
struct msm_file_private *ctx)
|
|
{
|
|
struct drm_device *dev = gpu->dev;
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
int i;
|
|
|
|
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
|
|
|
|
inactive_cancel(gpu);
|
|
|
|
list_add_tail(&submit->node, &gpu->submit_list);
|
|
|
|
msm_rd_dump_submit(submit);
|
|
|
|
update_sw_cntrs(gpu);
|
|
|
|
for (i = 0; i < submit->nr_bos; i++) {
|
|
struct msm_gem_object *msm_obj = submit->bos[i].obj;
|
|
uint32_t iova;
|
|
|
|
/* can't happen yet.. but when we add 2d support we'll have
|
|
* to deal w/ cross-ring synchronization:
|
|
*/
|
|
WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
|
|
|
|
/* submit takes a reference to the bo and iova until retired: */
|
|
drm_gem_object_reference(&msm_obj->base);
|
|
msm_gem_get_iova_locked(&msm_obj->base,
|
|
submit->gpu->id, &iova);
|
|
|
|
if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
|
|
msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
|
|
else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
|
|
msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
|
|
}
|
|
|
|
gpu->funcs->submit(gpu, submit, ctx);
|
|
priv->lastctx = ctx;
|
|
|
|
hangcheck_timer_reset(gpu);
|
|
}
|
|
|
|
/*
|
|
* Init/Cleanup:
|
|
*/
|
|
|
|
static irqreturn_t irq_handler(int irq, void *data)
|
|
{
|
|
struct msm_gpu *gpu = data;
|
|
return gpu->funcs->irq(gpu);
|
|
}
|
|
|
|
static const char *clk_names[] = {
|
|
"src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",
|
|
"alt_mem_iface_clk",
|
|
};
|
|
|
|
int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
|
|
const char *name, const char *ioname, const char *irqname, int ringsz)
|
|
{
|
|
struct iommu_domain *iommu;
|
|
int i, ret;
|
|
|
|
if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
|
|
gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
|
|
|
|
gpu->dev = drm;
|
|
gpu->funcs = funcs;
|
|
gpu->name = name;
|
|
gpu->inactive = true;
|
|
gpu->fctx = msm_fence_context_alloc(drm, name);
|
|
if (IS_ERR(gpu->fctx)) {
|
|
ret = PTR_ERR(gpu->fctx);
|
|
gpu->fctx = NULL;
|
|
goto fail;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&gpu->active_list);
|
|
INIT_WORK(&gpu->retire_work, retire_worker);
|
|
INIT_WORK(&gpu->inactive_work, inactive_worker);
|
|
INIT_WORK(&gpu->recover_work, recover_worker);
|
|
|
|
INIT_LIST_HEAD(&gpu->submit_list);
|
|
|
|
setup_timer(&gpu->inactive_timer, inactive_handler,
|
|
(unsigned long)gpu);
|
|
setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
|
|
(unsigned long)gpu);
|
|
|
|
spin_lock_init(&gpu->perf_lock);
|
|
|
|
BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks));
|
|
|
|
/* Map registers: */
|
|
gpu->mmio = msm_ioremap(pdev, ioname, name);
|
|
if (IS_ERR(gpu->mmio)) {
|
|
ret = PTR_ERR(gpu->mmio);
|
|
goto fail;
|
|
}
|
|
|
|
/* Get Interrupt: */
|
|
gpu->irq = platform_get_irq_byname(pdev, irqname);
|
|
if (gpu->irq < 0) {
|
|
ret = gpu->irq;
|
|
dev_err(drm->dev, "failed to get irq: %d\n", ret);
|
|
goto fail;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
|
|
IRQF_TRIGGER_HIGH, gpu->name, gpu);
|
|
if (ret) {
|
|
dev_err(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
|
|
goto fail;
|
|
}
|
|
|
|
/* Acquire clocks: */
|
|
for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
|
|
gpu->grp_clks[i] = devm_clk_get(&pdev->dev, clk_names[i]);
|
|
DBG("grp_clks[%s]: %p", clk_names[i], gpu->grp_clks[i]);
|
|
if (IS_ERR(gpu->grp_clks[i]))
|
|
gpu->grp_clks[i] = NULL;
|
|
}
|
|
|
|
gpu->ebi1_clk = devm_clk_get(&pdev->dev, "bus_clk");
|
|
DBG("ebi1_clk: %p", gpu->ebi1_clk);
|
|
if (IS_ERR(gpu->ebi1_clk))
|
|
gpu->ebi1_clk = NULL;
|
|
|
|
/* Acquire regulators: */
|
|
gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
|
|
DBG("gpu_reg: %p", gpu->gpu_reg);
|
|
if (IS_ERR(gpu->gpu_reg))
|
|
gpu->gpu_reg = NULL;
|
|
|
|
gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
|
|
DBG("gpu_cx: %p", gpu->gpu_cx);
|
|
if (IS_ERR(gpu->gpu_cx))
|
|
gpu->gpu_cx = NULL;
|
|
|
|
/* Setup IOMMU.. eventually we will (I think) do this once per context
|
|
* and have separate page tables per context. For now, to keep things
|
|
* simple and to get something working, just use a single address space:
|
|
*/
|
|
iommu = iommu_domain_alloc(&platform_bus_type);
|
|
if (iommu) {
|
|
dev_info(drm->dev, "%s: using IOMMU\n", name);
|
|
gpu->mmu = msm_iommu_new(&pdev->dev, iommu);
|
|
if (IS_ERR(gpu->mmu)) {
|
|
ret = PTR_ERR(gpu->mmu);
|
|
dev_err(drm->dev, "failed to init iommu: %d\n", ret);
|
|
gpu->mmu = NULL;
|
|
iommu_domain_free(iommu);
|
|
goto fail;
|
|
}
|
|
|
|
} else {
|
|
dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
|
|
}
|
|
gpu->id = msm_register_mmu(drm, gpu->mmu);
|
|
|
|
|
|
/* Create ringbuffer: */
|
|
mutex_lock(&drm->struct_mutex);
|
|
gpu->rb = msm_ringbuffer_new(gpu, ringsz);
|
|
mutex_unlock(&drm->struct_mutex);
|
|
if (IS_ERR(gpu->rb)) {
|
|
ret = PTR_ERR(gpu->rb);
|
|
gpu->rb = NULL;
|
|
dev_err(drm->dev, "could not create ringbuffer: %d\n", ret);
|
|
goto fail;
|
|
}
|
|
|
|
bs_init(gpu);
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
return ret;
|
|
}
|
|
|
|
void msm_gpu_cleanup(struct msm_gpu *gpu)
|
|
{
|
|
DBG("%s", gpu->name);
|
|
|
|
WARN_ON(!list_empty(&gpu->active_list));
|
|
|
|
bs_fini(gpu);
|
|
|
|
if (gpu->rb) {
|
|
if (gpu->rb_iova)
|
|
msm_gem_put_iova(gpu->rb->bo, gpu->id);
|
|
msm_ringbuffer_destroy(gpu->rb);
|
|
}
|
|
|
|
if (gpu->mmu)
|
|
gpu->mmu->funcs->destroy(gpu->mmu);
|
|
|
|
if (gpu->fctx)
|
|
msm_fence_context_free(gpu->fctx);
|
|
}
|