forked from Minki/linux
e2fce0a28d
The tegra DRM driver produces a harmless warning when built for NOMMU: drivers/gpu/drm/tegra/gem.c: In function 'tegra_drm_mmap': drivers/gpu/drm/tegra/gem.c:508:12: unused variable 'prot' This is because pgprot_writecombine() on ARM returns a constant and ignores its argument. The version in asm-generic doesn't have that problem, so let's use that one instead. We don't actually care about the value on NOMMU, and this is consistent with what some other architectures do. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
115 lines
2.6 KiB
C
115 lines
2.6 KiB
C
/*
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* arch/arm/include/asm/pgtable-nommu.h
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*
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* Copyright (C) 1995-2002 Russell King
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* Copyright (C) 2004 Hyok S. Choi
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASMARM_PGTABLE_NOMMU_H
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#define _ASMARM_PGTABLE_NOMMU_H
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#ifndef __ASSEMBLY__
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#include <linux/slab.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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/*
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* Trivial page table functions.
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*/
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#define pgd_present(pgd) (1)
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#define pgd_none(pgd) (0)
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#define pgd_bad(pgd) (0)
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#define pgd_clear(pgdp)
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#define kern_addr_valid(addr) (1)
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#define pmd_offset(a, b) ((void *)0)
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/* FIXME */
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/*
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* PMD_SHIFT determines the size of the area a second-level page table can map
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* PGDIR_SHIFT determines what a third-level page table entry can map
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*/
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#define PGDIR_SHIFT 21
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* FIXME */
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#define PAGE_NONE __pgprot(0)
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#define PAGE_SHARED __pgprot(0)
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#define PAGE_COPY __pgprot(0)
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#define PAGE_READONLY __pgprot(0)
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#define PAGE_KERNEL __pgprot(0)
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#define swapper_pg_dir ((pgd_t *) 0)
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#define __swp_type(x) (0)
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#define __swp_offset(x) (0)
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#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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typedef pte_t *pte_addr_t;
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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#define ZERO_PAGE(vaddr) (virt_to_page(0))
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/*
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* Mark the prot value as uncacheable and unbufferable.
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*/
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#define pgprot_noncached(prot) (prot)
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#define pgprot_writecombine(prot) (prot)
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#define pgprot_dmacoherent(prot) (prot)
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/*
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* These would be in other places but having them here reduces the diffs.
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*/
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extern unsigned int kobjsize(const void *objp);
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/*
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* No page table caches to initialise.
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*/
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#define pgtable_cache_init() do { } while (0)
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/*
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* All 32bit addresses are effectively valid for vmalloc...
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* Sort of meaningless for non-VM targets.
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*/
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#define VMALLOC_START 0UL
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#define VMALLOC_END 0xffffffffUL
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#define FIRST_USER_ADDRESS 0UL
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#include <asm-generic/pgtable.h>
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#else
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/*
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* dummy tlb and user structures.
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*/
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#define v3_tlb_fns (0)
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#define v4_tlb_fns (0)
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#define v4wb_tlb_fns (0)
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#define v4wbi_tlb_fns (0)
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#define v6wbi_tlb_fns (0)
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#define v7wbi_tlb_fns (0)
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#define v3_user_fns (0)
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#define v4_user_fns (0)
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#define v4_mc_user_fns (0)
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#define v4wb_user_fns (0)
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#define v4wt_user_fns (0)
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#define v6_user_fns (0)
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#define xscale_mc_user_fns (0)
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#endif /*__ASSEMBLY__*/
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#endif /* _ASMARM_PGTABLE_H */
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