forked from Minki/linux
c592e631bc
This patch is the addition of files for a new driver to handle the Realtek RTL8723AE wireless device. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Cc: <chaoming_li@realsil.com.cn> Signed-off-by: John W. Linville <linville@tuxdriver.com>
130 lines
4.0 KiB
C
130 lines
4.0 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "pwrseq.h"
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/* Description:
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* This routine deals with the Power Configuration CMD
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* parsing for RTL8723/RTL8188E Series IC.
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* Assumption:
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* We should follow specific format that was released from HW SD.
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*/
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bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
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u8 faversion, u8 interface_type,
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struct wlan_pwr_cfg pwrcfgcmd[])
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{
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struct wlan_pwr_cfg cfg_cmd = {0};
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bool polling_bit = false;
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u32 ary_idx = 0;
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u8 value = 0;
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u32 offset = 0;
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u32 polling_count = 0;
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u32 max_polling_cnt = 5000;
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do {
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cfg_cmd = pwrcfgcmd[ary_idx];
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), famsk(%#x),"
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"interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
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GET_PWR_CFG_OFFSET(cfg_cmd),
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GET_PWR_CFG_CUT_MASK(cfg_cmd),
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GET_PWR_CFG_FAB_MASK(cfg_cmd),
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GET_PWR_CFG_INTF_MASK(cfg_cmd),
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GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd),
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GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd));
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if ((GET_PWR_CFG_FAB_MASK(cfg_cmd)&faversion) &&
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(GET_PWR_CFG_CUT_MASK(cfg_cmd)&cut_version) &&
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(GET_PWR_CFG_INTF_MASK(cfg_cmd)&interface_type)) {
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switch (GET_PWR_CFG_CMD(cfg_cmd)) {
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case PWR_CMD_READ:
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
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break;
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case PWR_CMD_WRITE:
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
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offset = GET_PWR_CFG_OFFSET(cfg_cmd);
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/*Read the value from system register*/
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value = rtl_read_byte(rtlpriv, offset);
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value &= (~(GET_PWR_CFG_MASK(cfg_cmd)));
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value |= (GET_PWR_CFG_VALUE(cfg_cmd) &
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GET_PWR_CFG_MASK(cfg_cmd));
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/*Write the value back to sytem register*/
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rtl_write_byte(rtlpriv, offset, value);
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break;
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case PWR_CMD_POLLING:
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
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polling_bit = false;
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offset = GET_PWR_CFG_OFFSET(cfg_cmd);
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do {
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value = rtl_read_byte(rtlpriv, offset);
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value &= GET_PWR_CFG_MASK(cfg_cmd);
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if (value ==
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(GET_PWR_CFG_VALUE(cfg_cmd)
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& GET_PWR_CFG_MASK(cfg_cmd)))
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polling_bit = true;
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else
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udelay(10);
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if (polling_count++ > max_polling_cnt)
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return false;
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} while (!polling_bit);
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break;
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case PWR_CMD_DELAY:
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
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if (GET_PWR_CFG_VALUE(cfg_cmd) ==
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PWRSEQ_DELAY_US)
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udelay(GET_PWR_CFG_OFFSET(cfg_cmd));
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else
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mdelay(GET_PWR_CFG_OFFSET(cfg_cmd));
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break;
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case PWR_CMD_END:
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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"rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
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return true;
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default:
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RT_ASSERT(false,
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"rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
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break;
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}
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}
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ary_idx++;
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} while (1);
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return true;
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}
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