forked from Minki/linux
38912bdbde
This patch sanities the RX coe and adds the Type-1 Rx checksum offload engine (COE). So the RX COE can be passed through the platform but can be fixed at run-time in case of the core has the HW capability register. Also to support the Type-1 Rx COE the driver must append the HW checksum at the end of payload in case the Rx checksum engine was used to offload the HW checksum. This v2 version also fixes the IPC that has to be enabled and verified. Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Hacked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
235 lines
6.1 KiB
C
235 lines
6.1 KiB
C
/*******************************************************************************
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This contains the functions to handle the normal descriptors.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/stmmac.h>
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#include "common.h"
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#include "descs_com.h"
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static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p, void __iomem *ioaddr)
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{
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int ret = 0;
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struct net_device_stats *stats = (struct net_device_stats *)data;
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if (unlikely(p->des01.tx.error_summary)) {
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if (unlikely(p->des01.tx.underflow_error)) {
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x->tx_underflow++;
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stats->tx_fifo_errors++;
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}
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if (unlikely(p->des01.tx.no_carrier)) {
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x->tx_carrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely(p->des01.tx.loss_carrier)) {
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x->tx_losscarrier++;
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stats->tx_carrier_errors++;
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}
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if (unlikely((p->des01.tx.excessive_deferral) ||
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(p->des01.tx.excessive_collisions) ||
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(p->des01.tx.late_collision)))
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stats->collisions += p->des01.tx.collision_count;
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ret = -1;
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}
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if (p->des01.etx.vlan_frame) {
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CHIP_DBG(KERN_INFO "GMAC TX status: VLAN frame\n");
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x->tx_vlan++;
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}
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if (unlikely(p->des01.tx.deferred))
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x->tx_deferred++;
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return ret;
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}
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static int ndesc_get_tx_len(struct dma_desc *p)
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{
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return p->des01.tx.buffer1_size;
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}
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/* This function verifies if each incoming frame has some errors
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* and, if required, updates the multicast statistics.
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* In case of success, it returns good_frame because the GMAC device
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* is supposed to be able to compute the csum in HW. */
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static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
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struct dma_desc *p)
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{
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int ret = good_frame;
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struct net_device_stats *stats = (struct net_device_stats *)data;
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if (unlikely(p->des01.rx.last_descriptor == 0)) {
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pr_warning("ndesc Error: Oversized Ethernet "
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"frame spanned multiple buffers\n");
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stats->rx_length_errors++;
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return discard_frame;
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}
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if (unlikely(p->des01.rx.error_summary)) {
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if (unlikely(p->des01.rx.descriptor_error))
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x->rx_desc++;
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if (unlikely(p->des01.rx.sa_filter_fail))
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x->sa_filter_fail++;
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if (unlikely(p->des01.rx.overflow_error))
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x->overflow_error++;
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if (unlikely(p->des01.rx.ipc_csum_error))
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x->ipc_csum_error++;
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if (unlikely(p->des01.rx.collision)) {
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x->rx_collision++;
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stats->collisions++;
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}
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if (unlikely(p->des01.rx.crc_error)) {
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x->rx_crc++;
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stats->rx_crc_errors++;
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}
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ret = discard_frame;
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}
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if (unlikely(p->des01.rx.dribbling))
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x->dribbling_bit++;
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if (unlikely(p->des01.rx.length_error)) {
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x->rx_length++;
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ret = discard_frame;
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}
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if (unlikely(p->des01.rx.mii_error)) {
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x->rx_mii++;
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ret = discard_frame;
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}
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#ifdef STMMAC_VLAN_TAG_USED
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if (p->des01.rx.vlan_tag)
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x->vlan_tag++;
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#endif
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return ret;
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}
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static void ndesc_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
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int disable_rx_ic)
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{
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int i;
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for (i = 0; i < ring_size; i++) {
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p->des01.rx.own = 1;
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p->des01.rx.buffer1_size = BUF_SIZE_2KiB - 1;
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ndesc_rx_set_on_ring_chain(p, (i == ring_size - 1));
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if (disable_rx_ic)
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p->des01.rx.disable_ic = 1;
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p++;
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}
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}
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static void ndesc_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
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{
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int i;
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for (i = 0; i < ring_size; i++) {
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p->des01.tx.own = 0;
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ndesc_tx_set_on_ring_chain(p, (i == (ring_size - 1)));
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p++;
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}
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}
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static int ndesc_get_tx_owner(struct dma_desc *p)
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{
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return p->des01.tx.own;
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}
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static int ndesc_get_rx_owner(struct dma_desc *p)
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{
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return p->des01.rx.own;
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}
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static void ndesc_set_tx_owner(struct dma_desc *p)
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{
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p->des01.tx.own = 1;
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}
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static void ndesc_set_rx_owner(struct dma_desc *p)
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{
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p->des01.rx.own = 1;
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}
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static int ndesc_get_tx_ls(struct dma_desc *p)
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{
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return p->des01.tx.last_segment;
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}
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static void ndesc_release_tx_desc(struct dma_desc *p)
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{
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int ter = p->des01.tx.end_ring;
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memset(p, 0, offsetof(struct dma_desc, des2));
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ndesc_end_tx_desc(p, ter);
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}
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static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
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int csum_flag)
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{
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p->des01.tx.first_segment = is_fs;
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norm_set_tx_desc_len(p, len);
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if (likely(csum_flag))
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p->des01.tx.checksum_insertion = cic_full;
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}
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static void ndesc_clear_tx_ic(struct dma_desc *p)
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{
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p->des01.tx.interrupt = 0;
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}
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static void ndesc_close_tx_desc(struct dma_desc *p)
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{
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p->des01.tx.last_segment = 1;
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p->des01.tx.interrupt = 1;
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}
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static int ndesc_get_rx_frame_len(struct dma_desc *p, int rx_coe_type)
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{
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/* The type-1 checksum offload engines append the checksum at
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* the end of frame and the two bytes of checksum are added in
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* the length.
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* Adjust for that in the framelen for type-1 checksum offload
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* engines. */
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if (rx_coe_type == STMMAC_RX_COE_TYPE1)
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return p->des01.rx.frame_length - 2;
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else
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return p->des01.rx.frame_length;
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}
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const struct stmmac_desc_ops ndesc_ops = {
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.tx_status = ndesc_get_tx_status,
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.rx_status = ndesc_get_rx_status,
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.get_tx_len = ndesc_get_tx_len,
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.init_rx_desc = ndesc_init_rx_desc,
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.init_tx_desc = ndesc_init_tx_desc,
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.get_tx_owner = ndesc_get_tx_owner,
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.get_rx_owner = ndesc_get_rx_owner,
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.release_tx_desc = ndesc_release_tx_desc,
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.prepare_tx_desc = ndesc_prepare_tx_desc,
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.clear_tx_ic = ndesc_clear_tx_ic,
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.close_tx_desc = ndesc_close_tx_desc,
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.get_tx_ls = ndesc_get_tx_ls,
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.set_tx_owner = ndesc_set_tx_owner,
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.set_rx_owner = ndesc_set_rx_owner,
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.get_rx_frame_len = ndesc_get_rx_frame_len,
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};
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