3818f11740
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC documentation is the correct parent of DISP1 gate clocks. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> |
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| .. | ||
| clk-exynos4.c | ||
| clk-exynos5250.c | ||
| clk-exynos5420.c | ||
| clk-exynos5440.c | ||
| clk-exynos-audss.c | ||
| clk-pll.c | ||
| clk-pll.h | ||
| clk-s3c64xx.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||