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There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> |
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| .. | ||
| base.c | ||
| gf100.c | ||
| gk104.c | ||
| gm107.c | ||
| gm200.c | ||
| gp10b.c | ||
| gp100.c | ||
| gp102.c | ||
| Kbuild | ||
| priv.h | ||