forked from Minki/linux
2d93aee152
Enabling the oscillator consumes slightly more power (100uA)
but allows to make sure that we exit from L1 on time.
Not doing so might lead to a PCIe specification violation
since we might wake up from L1 at the wrong time.
This issue has been identified on 3160 and 7260 only.
On older NICs L1 off is not enabled, on newer NICs (7265),
the issue is fixed.
When the bug occurs the user sees that the NIC has
disappeared from the PCI bridge, any access to the device
returns 0xff.
This fixes:
https://bugzilla.kernel.org/show_bug.cgi?id=64541
and has been extensively discussed here:
http://markmail.org/thread/mfmpzqt3r333n4bo
Cc: stable@vger.kernel.org [3.10+]
Fixes: 99cd471423 ("iwlwifi: add 7000 series device configuration")
Reported-and-tested-by: wzyboy <wzyboy@wzyboy.org>
Reviewed-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
285 lines
11 KiB
C
285 lines
11 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef __iwl_prph_h__
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#define __iwl_prph_h__
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/*
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* Registers in this file are internal, not PCI bus memory mapped.
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* Driver accesses these via HBUS_TARG_PRPH_* registers.
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*/
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#define PRPH_BASE (0x00000)
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#define PRPH_END (0xFFFFF)
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/* APMG (power management) constants */
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#define APMG_BASE (PRPH_BASE + 0x3000)
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#define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
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#define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
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#define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
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#define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
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#define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
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#define APMG_RFKILL_REG (APMG_BASE + 0x0014)
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#define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
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#define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
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#define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)
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#define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)
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#define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
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#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
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#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
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#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
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#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
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#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
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#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
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#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
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#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
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#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
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#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
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#define APMG_RTC_INT_STT_RFKILL (0x10000000)
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/* Device system time */
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#define DEVICE_SYSTEM_TIME_REG 0xA0206C
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/* Device NMI register */
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#define DEVICE_SET_NMI_REG 0x00a01c30
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/*****************************************************************************
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* 7000/3000 series SHR DTS addresses *
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*****************************************************************************/
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#define SHR_MISC_WFM_DTS_EN (0x00a10024)
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#define DTSC_CFG_MODE (0x00a10604)
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#define DTSC_VREF_AVG (0x00a10648)
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#define DTSC_VREF5_AVG (0x00a1064c)
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#define DTSC_CFG_MODE_PERIODIC (0x2)
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#define DTSC_PTAT_AVG (0x00a10650)
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/**
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* Tx Scheduler
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*
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* The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
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* (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
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* host DRAM. It steers each frame's Tx command (which contains the frame
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* data) into one of up to 7 prioritized Tx DMA FIFO channels within the
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* device. A queue maps to only one (selectable by driver) Tx DMA channel,
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* but one DMA channel may take input from several queues.
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*
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* Tx DMA FIFOs have dedicated purposes.
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*
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* For 5000 series and up, they are used differently
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* (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
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*
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* 0 -- EDCA BK (background) frames, lowest priority
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* 1 -- EDCA BE (best effort) frames, normal priority
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* 2 -- EDCA VI (video) frames, higher priority
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* 3 -- EDCA VO (voice) and management frames, highest priority
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* 4 -- unused
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* 5 -- unused
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* 6 -- unused
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* 7 -- Commands
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*
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* Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
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* In addition, driver can map the remaining queues to Tx DMA/FIFO
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* channels 0-3 to support 11n aggregation via EDCA DMA channels.
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*
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* The driver sets up each queue to work in one of two modes:
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*
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* 1) Scheduler-Ack, in which the scheduler automatically supports a
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* block-ack (BA) window of up to 64 TFDs. In this mode, each queue
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* contains TFDs for a unique combination of Recipient Address (RA)
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* and Traffic Identifier (TID), that is, traffic of a given
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* Quality-Of-Service (QOS) priority, destined for a single station.
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*
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* In scheduler-ack mode, the scheduler keeps track of the Tx status of
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* each frame within the BA window, including whether it's been transmitted,
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* and whether it's been acknowledged by the receiving station. The device
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* automatically processes block-acks received from the receiving STA,
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* and reschedules un-acked frames to be retransmitted (successful
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* Tx completion may end up being out-of-order).
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*
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* The driver must maintain the queue's Byte Count table in host DRAM
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* for this mode.
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* This mode does not support fragmentation.
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*
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* 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
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* The device may automatically retry Tx, but will retry only one frame
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* at a time, until receiving ACK from receiving station, or reaching
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* retry limit and giving up.
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*
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* The command queue (#4/#9) must use this mode!
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* This mode does not require use of the Byte Count table in host DRAM.
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*
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* Driver controls scheduler operation via 3 means:
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* 1) Scheduler registers
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* 2) Shared scheduler data base in internal SRAM
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* 3) Shared data in host DRAM
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*
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* Initialization:
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*
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* When loading, driver should allocate memory for:
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* 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
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* 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
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* (1024 bytes for each queue).
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*
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* After receiving "Alive" response from uCode, driver must initialize
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* the scheduler (especially for queue #4/#9, the command queue, otherwise
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* the driver can't issue commands!):
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*/
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#define SCD_MEM_LOWER_BOUND (0x0000)
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/**
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* Max Tx window size is the max number of contiguous TFDs that the scheduler
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* can keep track of at one time when creating block-ack chains of frames.
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* Note that "64" matches the number of ack bits in a block-ack packet.
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*/
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#define SCD_WIN_SIZE 64
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#define SCD_FRAME_LIMIT 64
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#define SCD_TXFIFO_POS_TID (0)
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#define SCD_TXFIFO_POS_RA (4)
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#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
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/* agn SCD */
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#define SCD_QUEUE_STTS_REG_POS_TXF (0)
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#define SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
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#define SCD_QUEUE_STTS_REG_POS_WSL (4)
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#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
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#define SCD_QUEUE_STTS_REG_MSK (0x017F0000)
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#define SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
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#define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
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#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
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#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
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#define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
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#define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
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#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
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#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
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/* Context Data */
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#define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
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#define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
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/* Tx status */
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#define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
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#define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
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/* Translation Data */
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#define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
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#define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)
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#define SCD_CONTEXT_QUEUE_OFFSET(x)\
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(SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
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#define SCD_TX_STTS_QUEUE_OFFSET(x)\
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(SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
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#define SCD_TRANS_TBL_OFFSET_QUEUE(x) \
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((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
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#define SCD_BASE (PRPH_BASE + 0xa02c00)
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#define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)
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#define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)
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#define SCD_AIT (SCD_BASE + 0x0c)
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#define SCD_TXFACT (SCD_BASE + 0x10)
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#define SCD_ACTIVE (SCD_BASE + 0x14)
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#define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)
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#define SCD_CHAINEXT_EN (SCD_BASE + 0x244)
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#define SCD_AGGR_SEL (SCD_BASE + 0x248)
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#define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)
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static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)
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{
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if (chnl < 20)
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return SCD_BASE + 0x18 + chnl * 4;
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WARN_ON_ONCE(chnl >= 32);
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return SCD_BASE + 0x284 + (chnl - 20) * 4;
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}
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static inline unsigned int SCD_QUEUE_RDPTR(unsigned int chnl)
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{
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if (chnl < 20)
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return SCD_BASE + 0x68 + chnl * 4;
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WARN_ON_ONCE(chnl >= 32);
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return SCD_BASE + 0x2B4 + (chnl - 20) * 4;
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}
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static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)
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{
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if (chnl < 20)
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return SCD_BASE + 0x10c + chnl * 4;
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WARN_ON_ONCE(chnl >= 32);
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return SCD_BASE + 0x384 + (chnl - 20) * 4;
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}
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/*********************** END TX SCHEDULER *************************************/
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/* Oscillator clock */
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#define OSC_CLK (0xa04068)
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#define OSC_CLK_FORCE_CONTROL (0x8)
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#endif /* __iwl_prph_h__ */
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