forked from Minki/linux
43569814fa
Provides an options to use the ptp clock routed from the Altera FPGA fabric. Instead of the defalt eosc1 clock connected to the ARM HPS core. This setting affects all emacs in the core as the ptp clock is common. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Phil Reid <preid@electromag.com.au> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: David S. Miller <davem@davemloft.net>
306 lines
8.5 KiB
C
306 lines
8.5 KiB
C
/* Copyright Altera Corporation (C) 2014. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2,
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Adopted from dwmac-sti.c
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_net.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/stmmac.h>
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#include "stmmac.h"
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#include "stmmac_platform.h"
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
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#define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
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#define EMAC_SPLITTER_CTRL_REG 0x0
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#define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
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#define EMAC_SPLITTER_CTRL_SPEED_10 0x2
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#define EMAC_SPLITTER_CTRL_SPEED_100 0x3
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#define EMAC_SPLITTER_CTRL_SPEED_1000 0x0
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struct socfpga_dwmac {
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int interface;
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u32 reg_offset;
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u32 reg_shift;
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struct device *dev;
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struct regmap *sys_mgr_base_addr;
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struct reset_control *stmmac_rst;
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void __iomem *splitter_base;
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bool f2h_ptp_ref_clk;
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};
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static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
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{
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struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv;
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void __iomem *splitter_base = dwmac->splitter_base;
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u32 val;
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if (!splitter_base)
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return;
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val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
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val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
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switch (speed) {
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case 1000:
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val |= EMAC_SPLITTER_CTRL_SPEED_1000;
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break;
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case 100:
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val |= EMAC_SPLITTER_CTRL_SPEED_100;
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break;
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case 10:
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val |= EMAC_SPLITTER_CTRL_SPEED_10;
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break;
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default:
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return;
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}
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writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
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}
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static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
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{
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struct device_node *np = dev->of_node;
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struct regmap *sys_mgr_base_addr;
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u32 reg_offset, reg_shift;
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int ret;
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struct device_node *np_splitter;
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struct resource res_splitter;
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dwmac->stmmac_rst = devm_reset_control_get(dev,
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STMMAC_RESOURCE_NAME);
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if (IS_ERR(dwmac->stmmac_rst)) {
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dev_info(dev, "Could not get reset control!\n");
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if (PTR_ERR(dwmac->stmmac_rst) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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dwmac->stmmac_rst = NULL;
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}
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dwmac->interface = of_get_phy_mode(np);
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sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
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if (IS_ERR(sys_mgr_base_addr)) {
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dev_info(dev, "No sysmgr-syscon node found\n");
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return PTR_ERR(sys_mgr_base_addr);
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}
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ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset);
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if (ret) {
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dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
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return -EINVAL;
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}
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ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift);
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if (ret) {
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dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
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return -EINVAL;
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}
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dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
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np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
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if (np_splitter) {
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if (of_address_to_resource(np_splitter, 0, &res_splitter)) {
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dev_info(dev, "Missing emac splitter address\n");
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return -EINVAL;
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}
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dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
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if (IS_ERR(dwmac->splitter_base)) {
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dev_info(dev, "Failed to mapping emac splitter\n");
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return PTR_ERR(dwmac->splitter_base);
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}
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}
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dwmac->reg_offset = reg_offset;
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dwmac->reg_shift = reg_shift;
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dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
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dwmac->dev = dev;
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return 0;
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}
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static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
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{
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struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
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int phymode = dwmac->interface;
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u32 reg_offset = dwmac->reg_offset;
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u32 reg_shift = dwmac->reg_shift;
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u32 ctrl, val;
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switch (phymode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
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break;
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_GMII:
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val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
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break;
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default:
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dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
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return -EINVAL;
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}
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/* Overwrite val to GMII if splitter core is enabled. The phymode here
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* is the actual phy mode on phy hardware, but phy interface from
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* EMAC core is GMII.
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*/
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if (dwmac->splitter_base)
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val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
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regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
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ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
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ctrl |= val << reg_shift;
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if (dwmac->f2h_ptp_ref_clk)
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ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
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else
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ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
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regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
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return 0;
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}
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static void socfpga_dwmac_exit(struct platform_device *pdev, void *priv)
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{
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struct socfpga_dwmac *dwmac = priv;
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/* On socfpga platform exit, assert and hold reset to the
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* enet controller - the default state after a hard reset.
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*/
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if (dwmac->stmmac_rst)
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reset_control_assert(dwmac->stmmac_rst);
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}
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static int socfpga_dwmac_init(struct platform_device *pdev, void *priv)
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{
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struct socfpga_dwmac *dwmac = priv;
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struct net_device *ndev = platform_get_drvdata(pdev);
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struct stmmac_priv *stpriv = NULL;
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int ret = 0;
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if (ndev)
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stpriv = netdev_priv(ndev);
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/* Assert reset to the enet controller before changing the phy mode */
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if (dwmac->stmmac_rst)
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reset_control_assert(dwmac->stmmac_rst);
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/* Setup the phy mode in the system manager registers according to
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* devicetree configuration
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*/
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ret = socfpga_dwmac_setup(dwmac);
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/* Deassert reset for the phy configuration to be sampled by
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* the enet controller, and operation to start in requested mode
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*/
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if (dwmac->stmmac_rst)
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reset_control_deassert(dwmac->stmmac_rst);
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/* Before the enet controller is suspended, the phy is suspended.
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* This causes the phy clock to be gated. The enet controller is
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* resumed before the phy, so the clock is still gated "off" when
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* the enet controller is resumed. This code makes sure the phy
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* is "resumed" before reinitializing the enet controller since
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* the enet controller depends on an active phy clock to complete
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* a DMA reset. A DMA reset will "time out" if executed
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* with no phy clock input on the Synopsys enet controller.
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* Verified through Synopsys Case #8000711656.
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*
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* Note that the phy clock is also gated when the phy is isolated.
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* Phy "suspend" and "isolate" controls are located in phy basic
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* control register 0, and can be modified by the phy driver
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* framework.
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*/
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if (stpriv && stpriv->phydev)
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phy_resume(stpriv->phydev);
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return ret;
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}
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static int socfpga_dwmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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struct stmmac_resources stmmac_res;
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struct device *dev = &pdev->dev;
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int ret;
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struct socfpga_dwmac *dwmac;
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ret = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (ret)
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return ret;
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plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
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if (IS_ERR(plat_dat))
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return PTR_ERR(plat_dat);
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dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
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if (!dwmac)
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return -ENOMEM;
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ret = socfpga_dwmac_parse_data(dwmac, dev);
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if (ret) {
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dev_err(dev, "Unable to parse OF data\n");
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return ret;
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}
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ret = socfpga_dwmac_setup(dwmac);
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if (ret) {
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dev_err(dev, "couldn't setup SoC glue (%d)\n", ret);
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return ret;
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}
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plat_dat->bsp_priv = dwmac;
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plat_dat->init = socfpga_dwmac_init;
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plat_dat->exit = socfpga_dwmac_exit;
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plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
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ret = socfpga_dwmac_init(pdev, plat_dat->bsp_priv);
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if (ret)
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return ret;
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return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
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}
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static const struct of_device_id socfpga_dwmac_match[] = {
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{ .compatible = "altr,socfpga-stmmac" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
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static struct platform_driver socfpga_dwmac_driver = {
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.probe = socfpga_dwmac_probe,
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.remove = stmmac_pltfr_remove,
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.driver = {
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.name = "socfpga-dwmac",
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.pm = &stmmac_pltfr_pm_ops,
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.of_match_table = socfpga_dwmac_match,
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},
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};
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module_platform_driver(socfpga_dwmac_driver);
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MODULE_LICENSE("GPL v2");
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