27e117e4b0
Deep power save allows firmware/hardware to operate in a lower power state. And the deep power save mode depends on LPS mode. So, before entering deep PS, driver must first enter LPS mode. Under Deep PS, most of hardware functions are shutdown, driver will not be able to read/write registers and transfer data to the device. Hence TX path must be protected by each interface. Take PCI for example, DMA engine should be idle, and no nore activities on the PCI bus. If driver wants to operate on the device, such as register read/write, it must first acquire the mutex lock and wake up from Deep PS, otherwise the behavior is undefined. Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
218 lines
5.0 KiB
C
218 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTW_HCI_H__
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#define __RTW_HCI_H__
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/* ops for PCI, USB and SDIO */
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struct rtw_hci_ops {
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int (*tx)(struct rtw_dev *rtwdev,
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struct rtw_tx_pkt_info *pkt_info,
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struct sk_buff *skb);
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int (*setup)(struct rtw_dev *rtwdev);
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int (*start)(struct rtw_dev *rtwdev);
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void (*stop)(struct rtw_dev *rtwdev);
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void (*deep_ps)(struct rtw_dev *rtwdev, bool enter);
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int (*write_data_rsvd_page)(struct rtw_dev *rtwdev, u8 *buf, u32 size);
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int (*write_data_h2c)(struct rtw_dev *rtwdev, u8 *buf, u32 size);
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u8 (*read8)(struct rtw_dev *rtwdev, u32 addr);
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u16 (*read16)(struct rtw_dev *rtwdev, u32 addr);
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u32 (*read32)(struct rtw_dev *rtwdev, u32 addr);
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void (*write8)(struct rtw_dev *rtwdev, u32 addr, u8 val);
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void (*write16)(struct rtw_dev *rtwdev, u32 addr, u16 val);
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void (*write32)(struct rtw_dev *rtwdev, u32 addr, u32 val);
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};
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static inline int rtw_hci_tx(struct rtw_dev *rtwdev,
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struct rtw_tx_pkt_info *pkt_info,
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struct sk_buff *skb)
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{
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return rtwdev->hci.ops->tx(rtwdev, pkt_info, skb);
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}
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static inline int rtw_hci_setup(struct rtw_dev *rtwdev)
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{
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return rtwdev->hci.ops->setup(rtwdev);
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}
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static inline int rtw_hci_start(struct rtw_dev *rtwdev)
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{
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return rtwdev->hci.ops->start(rtwdev);
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}
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static inline void rtw_hci_stop(struct rtw_dev *rtwdev)
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{
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rtwdev->hci.ops->stop(rtwdev);
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}
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static inline void rtw_hci_deep_ps(struct rtw_dev *rtwdev, bool enter)
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{
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rtwdev->hci.ops->deep_ps(rtwdev, enter);
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}
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static inline int
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rtw_hci_write_data_rsvd_page(struct rtw_dev *rtwdev, u8 *buf, u32 size)
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{
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return rtwdev->hci.ops->write_data_rsvd_page(rtwdev, buf, size);
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}
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static inline int
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rtw_hci_write_data_h2c(struct rtw_dev *rtwdev, u8 *buf, u32 size)
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{
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return rtwdev->hci.ops->write_data_h2c(rtwdev, buf, size);
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}
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static inline u8 rtw_read8(struct rtw_dev *rtwdev, u32 addr)
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{
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return rtwdev->hci.ops->read8(rtwdev, addr);
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}
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static inline u16 rtw_read16(struct rtw_dev *rtwdev, u32 addr)
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{
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return rtwdev->hci.ops->read16(rtwdev, addr);
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}
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static inline u32 rtw_read32(struct rtw_dev *rtwdev, u32 addr)
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{
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return rtwdev->hci.ops->read32(rtwdev, addr);
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}
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static inline void rtw_write8(struct rtw_dev *rtwdev, u32 addr, u8 val)
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{
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rtwdev->hci.ops->write8(rtwdev, addr, val);
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}
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static inline void rtw_write16(struct rtw_dev *rtwdev, u32 addr, u16 val)
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{
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rtwdev->hci.ops->write16(rtwdev, addr, val);
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}
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static inline void rtw_write32(struct rtw_dev *rtwdev, u32 addr, u32 val)
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{
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rtwdev->hci.ops->write32(rtwdev, addr, val);
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}
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static inline void rtw_write8_set(struct rtw_dev *rtwdev, u32 addr, u8 bit)
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{
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u8 val;
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val = rtw_read8(rtwdev, addr);
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rtw_write8(rtwdev, addr, val | bit);
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}
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static inline void rtw_write16_set(struct rtw_dev *rtwdev, u32 addr, u16 bit)
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{
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u16 val;
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val = rtw_read16(rtwdev, addr);
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rtw_write16(rtwdev, addr, val | bit);
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}
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static inline void rtw_write32_set(struct rtw_dev *rtwdev, u32 addr, u32 bit)
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{
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u32 val;
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val = rtw_read32(rtwdev, addr);
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rtw_write32(rtwdev, addr, val | bit);
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}
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static inline void rtw_write8_clr(struct rtw_dev *rtwdev, u32 addr, u8 bit)
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{
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u8 val;
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val = rtw_read8(rtwdev, addr);
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rtw_write8(rtwdev, addr, val & ~bit);
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}
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static inline void rtw_write16_clr(struct rtw_dev *rtwdev, u32 addr, u16 bit)
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{
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u16 val;
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val = rtw_read16(rtwdev, addr);
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rtw_write16(rtwdev, addr, val & ~bit);
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}
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static inline void rtw_write32_clr(struct rtw_dev *rtwdev, u32 addr, u32 bit)
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{
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u32 val;
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val = rtw_read32(rtwdev, addr);
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rtw_write32(rtwdev, addr, val & ~bit);
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}
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static inline u32
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rtw_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
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u32 addr, u32 mask)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&rtwdev->rf_lock, flags);
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val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
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spin_unlock_irqrestore(&rtwdev->rf_lock, flags);
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return val;
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}
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static inline void
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rtw_write_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
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u32 addr, u32 mask, u32 data)
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{
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unsigned long flags;
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spin_lock_irqsave(&rtwdev->rf_lock, flags);
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rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
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spin_unlock_irqrestore(&rtwdev->rf_lock, flags);
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}
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static inline u32
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rtw_read32_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask)
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{
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u32 shift = __ffs(mask);
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u32 orig;
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u32 ret;
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orig = rtw_read32(rtwdev, addr);
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ret = (orig & mask) >> shift;
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return ret;
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}
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static inline void
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rtw_write32_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
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{
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u32 shift = __ffs(mask);
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u32 orig;
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u32 set;
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WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
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orig = rtw_read32(rtwdev, addr);
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set = (orig & ~mask) | ((data << shift) & mask);
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rtw_write32(rtwdev, addr, set);
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}
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static inline void
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rtw_write8_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u8 data)
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{
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u32 shift;
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u8 orig, set;
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mask &= 0xff;
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shift = __ffs(mask);
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orig = rtw_read8(rtwdev, addr);
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set = (orig & ~mask) | ((data << shift) & mask);
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rtw_write8(rtwdev, addr, set);
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}
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static inline enum rtw_hci_type rtw_hci_type(struct rtw_dev *rtwdev)
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{
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return rtwdev->hci.type;
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}
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#endif
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