Madhav Chauhan 372610f3c8 drm/i915/icl: Define TRANS_CONF register for DSI ... This patch defines TRANS_CONF registers for DSI ports 0 and 1. Bitfields of these registers used for enabling and reading the current state of transcoder. v2: Add blank line before comment v3 by Jani: - Move DSI specific .pipe_offsets to GEN11_FEATURES - Macro placement and comment juggling Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3aa11e41ea0d4eb434423cc5ddf0a63b19d54deb.1539613303.git.jani.nikula@intel.com		2018-10-22 15:14:47 +03:00
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drm	drm/i915/icl: Define TRANS_CONF register for DSI	2018-10-22 15:14:47 +03:00
host1x	gpu: host1x: Check whether size of unpin isn't 0	2018-07-09 10:31:30 +02:00
ipu-v3	drm pull for 4.19-rc1	2018-08-15 17:39:07 -07:00
vga	vga_switcheroo: set audio client id according to bound GPU id	2018-07-17 11:12:00 +02:00
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