forked from Minki/linux
f9c56536d5
The etraxfs gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright <julia@ni.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
475 lines
11 KiB
C
475 lines
11 KiB
C
#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/gpio/driver.h>
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#include <linux/of_gpio.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#define ETRAX_FS_rw_pa_dout 0
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#define ETRAX_FS_r_pa_din 4
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#define ETRAX_FS_rw_pa_oe 8
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#define ETRAX_FS_rw_intr_cfg 12
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#define ETRAX_FS_rw_intr_mask 16
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#define ETRAX_FS_rw_ack_intr 20
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#define ETRAX_FS_r_intr 24
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#define ETRAX_FS_r_masked_intr 28
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#define ETRAX_FS_rw_pb_dout 32
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#define ETRAX_FS_r_pb_din 36
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#define ETRAX_FS_rw_pb_oe 40
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#define ETRAX_FS_rw_pc_dout 48
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#define ETRAX_FS_r_pc_din 52
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#define ETRAX_FS_rw_pc_oe 56
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#define ETRAX_FS_rw_pd_dout 64
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#define ETRAX_FS_r_pd_din 68
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#define ETRAX_FS_rw_pd_oe 72
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#define ETRAX_FS_rw_pe_dout 80
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#define ETRAX_FS_r_pe_din 84
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#define ETRAX_FS_rw_pe_oe 88
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#define ARTPEC3_r_pa_din 0
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#define ARTPEC3_rw_pa_dout 4
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#define ARTPEC3_rw_pa_oe 8
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#define ARTPEC3_r_pb_din 44
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#define ARTPEC3_rw_pb_dout 48
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#define ARTPEC3_rw_pb_oe 52
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#define ARTPEC3_r_pc_din 88
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#define ARTPEC3_rw_pc_dout 92
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#define ARTPEC3_rw_pc_oe 96
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#define ARTPEC3_r_pd_din 116
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#define ARTPEC3_rw_intr_cfg 120
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#define ARTPEC3_rw_intr_pins 124
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#define ARTPEC3_rw_intr_mask 128
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#define ARTPEC3_rw_ack_intr 132
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#define ARTPEC3_r_masked_intr 140
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#define GIO_CFG_OFF 0
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#define GIO_CFG_HI 1
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#define GIO_CFG_LO 2
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#define GIO_CFG_SET 3
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#define GIO_CFG_POSEDGE 5
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#define GIO_CFG_NEGEDGE 6
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#define GIO_CFG_ANYEDGE 7
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struct etraxfs_gpio_info;
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struct etraxfs_gpio_block {
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raw_spinlock_t lock;
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u32 mask;
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u32 cfg;
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u32 pins;
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unsigned int group[8];
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void __iomem *regs;
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const struct etraxfs_gpio_info *info;
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};
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struct etraxfs_gpio_chip {
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struct gpio_chip gc;
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struct etraxfs_gpio_block *block;
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};
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struct etraxfs_gpio_port {
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const char *label;
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unsigned int oe;
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unsigned int dout;
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unsigned int din;
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unsigned int ngpio;
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};
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struct etraxfs_gpio_info {
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unsigned int num_ports;
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const struct etraxfs_gpio_port *ports;
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unsigned int rw_ack_intr;
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unsigned int rw_intr_mask;
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unsigned int rw_intr_cfg;
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unsigned int rw_intr_pins;
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unsigned int r_masked_intr;
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};
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static const struct etraxfs_gpio_port etraxfs_gpio_etraxfs_ports[] = {
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{
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.label = "A",
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.ngpio = 8,
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.oe = ETRAX_FS_rw_pa_oe,
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.dout = ETRAX_FS_rw_pa_dout,
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.din = ETRAX_FS_r_pa_din,
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},
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{
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.label = "B",
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.ngpio = 18,
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.oe = ETRAX_FS_rw_pb_oe,
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.dout = ETRAX_FS_rw_pb_dout,
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.din = ETRAX_FS_r_pb_din,
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},
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{
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.label = "C",
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.ngpio = 18,
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.oe = ETRAX_FS_rw_pc_oe,
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.dout = ETRAX_FS_rw_pc_dout,
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.din = ETRAX_FS_r_pc_din,
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},
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{
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.label = "D",
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.ngpio = 18,
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.oe = ETRAX_FS_rw_pd_oe,
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.dout = ETRAX_FS_rw_pd_dout,
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.din = ETRAX_FS_r_pd_din,
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},
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{
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.label = "E",
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.ngpio = 18,
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.oe = ETRAX_FS_rw_pe_oe,
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.dout = ETRAX_FS_rw_pe_dout,
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.din = ETRAX_FS_r_pe_din,
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},
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};
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static const struct etraxfs_gpio_info etraxfs_gpio_etraxfs = {
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.num_ports = ARRAY_SIZE(etraxfs_gpio_etraxfs_ports),
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.ports = etraxfs_gpio_etraxfs_ports,
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.rw_ack_intr = ETRAX_FS_rw_ack_intr,
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.rw_intr_mask = ETRAX_FS_rw_intr_mask,
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.rw_intr_cfg = ETRAX_FS_rw_intr_cfg,
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.r_masked_intr = ETRAX_FS_r_masked_intr,
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};
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static const struct etraxfs_gpio_port etraxfs_gpio_artpec3_ports[] = {
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{
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.label = "A",
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.ngpio = 32,
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.oe = ARTPEC3_rw_pa_oe,
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.dout = ARTPEC3_rw_pa_dout,
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.din = ARTPEC3_r_pa_din,
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},
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{
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.label = "B",
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.ngpio = 32,
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.oe = ARTPEC3_rw_pb_oe,
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.dout = ARTPEC3_rw_pb_dout,
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.din = ARTPEC3_r_pb_din,
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},
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{
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.label = "C",
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.ngpio = 16,
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.oe = ARTPEC3_rw_pc_oe,
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.dout = ARTPEC3_rw_pc_dout,
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.din = ARTPEC3_r_pc_din,
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},
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{
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.label = "D",
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.ngpio = 32,
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.din = ARTPEC3_r_pd_din,
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},
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};
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static const struct etraxfs_gpio_info etraxfs_gpio_artpec3 = {
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.num_ports = ARRAY_SIZE(etraxfs_gpio_artpec3_ports),
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.ports = etraxfs_gpio_artpec3_ports,
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.rw_ack_intr = ARTPEC3_rw_ack_intr,
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.rw_intr_mask = ARTPEC3_rw_intr_mask,
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.rw_intr_cfg = ARTPEC3_rw_intr_cfg,
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.r_masked_intr = ARTPEC3_r_masked_intr,
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.rw_intr_pins = ARTPEC3_rw_intr_pins,
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};
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static unsigned int etraxfs_gpio_chip_to_port(struct gpio_chip *gc)
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{
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return gc->label[0] - 'A';
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}
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static int etraxfs_gpio_of_xlate(struct gpio_chip *gc,
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const struct of_phandle_args *gpiospec,
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u32 *flags)
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{
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/*
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* Port numbers are A to E, and the properties are integers, so we
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* specify them as 0xA - 0xE.
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*/
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if (etraxfs_gpio_chip_to_port(gc) + 0xA != gpiospec->args[2])
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return -EINVAL;
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return of_gpio_simple_xlate(gc, gpiospec, flags);
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}
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static const struct of_device_id etraxfs_gpio_of_table[] = {
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{
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.compatible = "axis,etraxfs-gio",
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.data = &etraxfs_gpio_etraxfs,
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},
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{
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.compatible = "axis,artpec3-gio",
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.data = &etraxfs_gpio_artpec3,
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},
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{},
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};
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static unsigned int etraxfs_gpio_to_group_irq(unsigned int gpio)
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{
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return gpio % 8;
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}
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static unsigned int etraxfs_gpio_to_group_pin(struct etraxfs_gpio_chip *chip,
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unsigned int gpio)
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{
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return 4 * etraxfs_gpio_chip_to_port(&chip->gc) + gpio / 8;
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}
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static void etraxfs_gpio_irq_ack(struct irq_data *d)
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{
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struct etraxfs_gpio_chip *chip =
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gpiochip_get_data(irq_data_get_irq_chip_data(d));
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struct etraxfs_gpio_block *block = chip->block;
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unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
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writel(BIT(grpirq), block->regs + block->info->rw_ack_intr);
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}
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static void etraxfs_gpio_irq_mask(struct irq_data *d)
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{
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struct etraxfs_gpio_chip *chip =
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gpiochip_get_data(irq_data_get_irq_chip_data(d));
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struct etraxfs_gpio_block *block = chip->block;
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unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
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raw_spin_lock(&block->lock);
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block->mask &= ~BIT(grpirq);
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writel(block->mask, block->regs + block->info->rw_intr_mask);
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raw_spin_unlock(&block->lock);
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}
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static void etraxfs_gpio_irq_unmask(struct irq_data *d)
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{
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struct etraxfs_gpio_chip *chip =
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gpiochip_get_data(irq_data_get_irq_chip_data(d));
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struct etraxfs_gpio_block *block = chip->block;
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unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
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raw_spin_lock(&block->lock);
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block->mask |= BIT(grpirq);
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writel(block->mask, block->regs + block->info->rw_intr_mask);
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raw_spin_unlock(&block->lock);
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}
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static int etraxfs_gpio_irq_set_type(struct irq_data *d, u32 type)
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{
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struct etraxfs_gpio_chip *chip =
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gpiochip_get_data(irq_data_get_irq_chip_data(d));
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struct etraxfs_gpio_block *block = chip->block;
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unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
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u32 cfg;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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cfg = GIO_CFG_POSEDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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cfg = GIO_CFG_NEGEDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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cfg = GIO_CFG_ANYEDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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cfg = GIO_CFG_LO;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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cfg = GIO_CFG_HI;
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break;
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default:
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return -EINVAL;
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}
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raw_spin_lock(&block->lock);
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block->cfg &= ~(0x7 << (grpirq * 3));
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block->cfg |= (cfg << (grpirq * 3));
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writel(block->cfg, block->regs + block->info->rw_intr_cfg);
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raw_spin_unlock(&block->lock);
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return 0;
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}
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static int etraxfs_gpio_irq_request_resources(struct irq_data *d)
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{
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struct etraxfs_gpio_chip *chip =
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gpiochip_get_data(irq_data_get_irq_chip_data(d));
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struct etraxfs_gpio_block *block = chip->block;
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unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
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int ret = -EBUSY;
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raw_spin_lock(&block->lock);
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if (block->group[grpirq])
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goto out;
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ret = gpiochip_lock_as_irq(&chip->gc, d->hwirq);
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if (ret)
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goto out;
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block->group[grpirq] = d->irq;
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if (block->info->rw_intr_pins) {
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unsigned int pin = etraxfs_gpio_to_group_pin(chip, d->hwirq);
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block->pins &= ~(0xf << (grpirq * 4));
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block->pins |= (pin << (grpirq * 4));
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writel(block->pins, block->regs + block->info->rw_intr_pins);
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}
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out:
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raw_spin_unlock(&block->lock);
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return ret;
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}
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static void etraxfs_gpio_irq_release_resources(struct irq_data *d)
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{
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struct etraxfs_gpio_chip *chip =
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gpiochip_get_data(irq_data_get_irq_chip_data(d));
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struct etraxfs_gpio_block *block = chip->block;
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unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq);
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raw_spin_lock(&block->lock);
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block->group[grpirq] = 0;
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gpiochip_unlock_as_irq(&chip->gc, d->hwirq);
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raw_spin_unlock(&block->lock);
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}
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static struct irq_chip etraxfs_gpio_irq_chip = {
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.name = "gpio-etraxfs",
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.irq_ack = etraxfs_gpio_irq_ack,
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.irq_mask = etraxfs_gpio_irq_mask,
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.irq_unmask = etraxfs_gpio_irq_unmask,
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.irq_set_type = etraxfs_gpio_irq_set_type,
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.irq_request_resources = etraxfs_gpio_irq_request_resources,
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.irq_release_resources = etraxfs_gpio_irq_release_resources,
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};
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static irqreturn_t etraxfs_gpio_interrupt(int irq, void *dev_id)
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{
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struct etraxfs_gpio_block *block = dev_id;
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unsigned long intr = readl(block->regs + block->info->r_masked_intr);
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int bit;
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for_each_set_bit(bit, &intr, 8)
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generic_handle_irq(block->group[bit]);
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return IRQ_RETVAL(intr & 0xff);
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}
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static int etraxfs_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct etraxfs_gpio_info *info;
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const struct of_device_id *match;
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struct etraxfs_gpio_block *block;
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struct etraxfs_gpio_chip *chips;
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struct resource *res, *irq;
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bool allportsirq = false;
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void __iomem *regs;
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int ret;
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int i;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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match = of_match_node(etraxfs_gpio_of_table, dev->of_node);
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if (!match)
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return -EINVAL;
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info = match->data;
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chips = devm_kzalloc(dev, sizeof(*chips) * info->num_ports, GFP_KERNEL);
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if (!chips)
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return -ENOMEM;
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!irq)
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return -EINVAL;
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block = devm_kzalloc(dev, sizeof(*block), GFP_KERNEL);
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if (!block)
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return -ENOMEM;
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raw_spin_lock_init(&block->lock);
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block->regs = regs;
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block->info = info;
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writel(0, block->regs + info->rw_intr_mask);
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writel(0, block->regs + info->rw_intr_cfg);
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if (info->rw_intr_pins) {
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allportsirq = true;
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writel(0, block->regs + info->rw_intr_pins);
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}
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ret = devm_request_irq(dev, irq->start, etraxfs_gpio_interrupt,
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IRQF_SHARED, dev_name(dev), block);
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if (ret) {
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dev_err(dev, "Unable to request irq %d\n", ret);
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return ret;
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}
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for (i = 0; i < info->num_ports; i++) {
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struct etraxfs_gpio_chip *chip = &chips[i];
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struct gpio_chip *gc = &chip->gc;
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const struct etraxfs_gpio_port *port = &info->ports[i];
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unsigned long flags = BGPIOF_READ_OUTPUT_REG_SET;
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void __iomem *dat = regs + port->din;
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void __iomem *set = regs + port->dout;
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void __iomem *dirout = regs + port->oe;
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chip->block = block;
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if (dirout == set) {
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dirout = set = NULL;
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flags = BGPIOF_NO_OUTPUT;
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}
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ret = bgpio_init(gc, dev, 4,
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dat, set, NULL, dirout, NULL,
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flags);
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if (ret) {
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dev_err(dev, "Unable to init port %s\n",
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port->label);
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continue;
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}
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gc->ngpio = port->ngpio;
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gc->label = port->label;
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gc->of_node = dev->of_node;
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gc->of_gpio_n_cells = 3;
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gc->of_xlate = etraxfs_gpio_of_xlate;
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ret = gpiochip_add_data(gc, chip);
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if (ret) {
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dev_err(dev, "Unable to register port %s\n",
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gc->label);
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continue;
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}
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if (i > 0 && !allportsirq)
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continue;
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ret = gpiochip_irqchip_add(gc, &etraxfs_gpio_irq_chip, 0,
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handle_level_irq, IRQ_TYPE_NONE);
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if (ret) {
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dev_err(dev, "Unable to add irqchip to port %s\n",
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gc->label);
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}
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}
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return 0;
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}
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static struct platform_driver etraxfs_gpio_driver = {
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.driver = {
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.name = "etraxfs-gpio",
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.of_match_table = of_match_ptr(etraxfs_gpio_of_table),
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},
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.probe = etraxfs_gpio_probe,
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};
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builtin_platform_driver(etraxfs_gpio_driver);
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