Rajendra Nayak 357c3f0a6c clk: Add support for rate table based dividers ... Some divider clks do not have any obvious relationship between the divider and the value programmed in the register. For instance, say a value of 1 could signify divide by 6 and a value of 2 could signify divide by 4 etc. Also there are dividers where not all values possible based on the bitfield width are valid. For instance a 3 bit wide bitfield can be used to program a value from 0 to 7. However its possible that only 0 to 4 are valid values. All these cases need the platform code to pass a simple table of divider/value tuple, so the framework knows the exact value to be written based on the divider calculation and can also do better error checking. This patch adds support for such rate table based dividers and as part of the support adds a new registration function 'clk_register_divider_table()' and a new macro for static definition 'DEFINE_CLK_DIVIDER_TABLE'. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>		2012-07-11 15:36:42 -07:00
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mxs	clk: mxs: fix clock lookup after freeing init memory	2012-06-25 16:51:48 -07:00
spear	clk: SPEAr600: Fix ethernet clock name for DT based probing	2012-06-25 16:51:47 -07:00
clk-divider.c	clk: Add support for rate table based dividers	2012-07-11 15:36:42 -07:00
clk-fixed-factor.c	clk: add a fixed factor clock	2012-05-08 14:13:25 -07:00
clk-fixed-rate.c	clk: Use a separate struct for holding init data.	2012-05-01 18:13:20 -07:00
clk-gate.c	clk: Use a separate struct for holding init data.	2012-05-01 18:13:20 -07:00
clk-mux.c	clk: mux: assign init data	2012-05-08 14:13:07 -07:00
clk.c	clk: fix parent validation in __clk_set_parent()	2012-07-03 12:05:14 -07:00
clkdev.c	CLKDEV: provide helpers for common clock framework	2012-05-02 09:30:32 +01:00
Kconfig	clk: remove COMMON_CLK_DISABLE_UNUSED	2012-05-08 14:12:42 -07:00
Makefile	Merge branch 'spear/clock' into next/clock	2012-05-13 00:11:06 +02:00