forked from Minki/linux
595 lines
14 KiB
C
595 lines
14 KiB
C
/*
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* arch/arm/mach-ixp4xx/common.c
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*
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* Generic code shared across all IXP4XX platforms
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*
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* Maintainer: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2002 (c) Intel Corporation
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* Copyright 2003-2004 (c) MontaVista, Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/platform_device.h>
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#include <linux/serial_core.h>
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#include <linux/gpio.h>
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#include <mach/udc.h>
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/irq.h>
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#include <asm/sched_clock.h>
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#include <asm/system_misc.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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static void __init ixp4xx_clocksource_init(void);
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static void __init ixp4xx_clockevent_init(void);
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static struct clock_event_device clockevent_ixp4xx;
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/*************************************************************************
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* IXP4xx chipset I/O mapping
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*************************************************************************/
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static struct map_desc ixp4xx_io_desc[] __initdata = {
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{ /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
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.virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
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.length = IXP4XX_PERIPHERAL_REGION_SIZE,
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.type = MT_DEVICE
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}, { /* Expansion Bus Config Registers */
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.virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
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.length = IXP4XX_EXP_CFG_REGION_SIZE,
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.type = MT_DEVICE
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}, { /* PCI Registers */
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.virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
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.length = IXP4XX_PCI_CFG_REGION_SIZE,
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.type = MT_DEVICE
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}, { /* Queue Manager */
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.virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
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.length = IXP4XX_QMGR_REGION_SIZE,
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.type = MT_DEVICE
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},
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};
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void __init ixp4xx_map_io(void)
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{
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iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
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}
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/*************************************************************************
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* IXP4xx chipset IRQ handling
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*
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* TODO: GPIO IRQs should be marked invalid until the user of the IRQ
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* (be it PCI or something else) configures that GPIO line
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* as an IRQ.
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**************************************************************************/
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enum ixp4xx_irq_type {
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IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
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};
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/* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
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static unsigned long long ixp4xx_irq_edge = 0;
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/*
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* IRQ -> GPIO mapping table
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*/
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static signed char irq2gpio[32] = {
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-1, -1, -1, -1, -1, -1, 0, 1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, 2, 3, 4, 5, 6,
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7, 8, 9, 10, 11, 12, -1, -1,
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};
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static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
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{
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int irq;
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for (irq = 0; irq < 32; irq++) {
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if (irq2gpio[irq] == gpio)
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return irq;
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}
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return -EINVAL;
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}
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int irq_to_gpio(unsigned int irq)
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{
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int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
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if (gpio == -1)
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return -EINVAL;
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return gpio;
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}
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EXPORT_SYMBOL(irq_to_gpio);
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static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
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{
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int line = irq2gpio[d->irq];
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u32 int_style;
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enum ixp4xx_irq_type irq_type;
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volatile u32 *int_reg;
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/*
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* Only for GPIO IRQs
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*/
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if (line < 0)
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return -EINVAL;
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switch (type){
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case IRQ_TYPE_EDGE_BOTH:
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int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
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irq_type = IXP4XX_IRQ_EDGE;
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break;
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case IRQ_TYPE_EDGE_RISING:
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int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
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irq_type = IXP4XX_IRQ_EDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
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irq_type = IXP4XX_IRQ_EDGE;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
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irq_type = IXP4XX_IRQ_LEVEL;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
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irq_type = IXP4XX_IRQ_LEVEL;
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break;
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default:
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return -EINVAL;
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}
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if (irq_type == IXP4XX_IRQ_EDGE)
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ixp4xx_irq_edge |= (1 << d->irq);
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else
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ixp4xx_irq_edge &= ~(1 << d->irq);
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if (line >= 8) { /* pins 8-15 */
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line -= 8;
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int_reg = IXP4XX_GPIO_GPIT2R;
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} else { /* pins 0-7 */
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int_reg = IXP4XX_GPIO_GPIT1R;
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}
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/* Clear the style for the appropriate pin */
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*int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
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(line * IXP4XX_GPIO_STYLE_SIZE));
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*IXP4XX_GPIO_GPISR = (1 << line);
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/* Set the new style */
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*int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
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/* Configure the line as an input */
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gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
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return 0;
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}
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static void ixp4xx_irq_mask(struct irq_data *d)
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{
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if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
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*IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
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else
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*IXP4XX_ICMR &= ~(1 << d->irq);
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}
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static void ixp4xx_irq_ack(struct irq_data *d)
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{
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int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
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if (line >= 0)
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*IXP4XX_GPIO_GPISR = (1 << line);
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}
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/*
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* Level triggered interrupts on GPIO lines can only be cleared when the
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* interrupt condition disappears.
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*/
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static void ixp4xx_irq_unmask(struct irq_data *d)
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{
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if (!(ixp4xx_irq_edge & (1 << d->irq)))
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ixp4xx_irq_ack(d);
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if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
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*IXP4XX_ICMR2 |= (1 << (d->irq - 32));
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else
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*IXP4XX_ICMR |= (1 << d->irq);
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}
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static struct irq_chip ixp4xx_irq_chip = {
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.name = "IXP4xx",
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.irq_ack = ixp4xx_irq_ack,
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.irq_mask = ixp4xx_irq_mask,
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.irq_unmask = ixp4xx_irq_unmask,
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.irq_set_type = ixp4xx_set_irq_type,
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};
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void __init ixp4xx_init_irq(void)
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{
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int i = 0;
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/*
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* ixp4xx does not implement the XScale PWRMODE register
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* so it must not call cpu_do_idle().
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*/
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disable_hlt();
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/* Route all sources to IRQ instead of FIQ */
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*IXP4XX_ICLR = 0x0;
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/* Disable all interrupt */
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*IXP4XX_ICMR = 0x0;
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if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
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/* Route upper 32 sources to IRQ instead of FIQ */
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*IXP4XX_ICLR2 = 0x00;
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/* Disable upper 32 interrupts */
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*IXP4XX_ICMR2 = 0x00;
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}
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/* Default to all level triggered */
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for(i = 0; i < NR_IRQS; i++) {
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irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
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handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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}
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/*************************************************************************
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* IXP4xx timer tick
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* We use OS timer1 on the CPU for the timer tick and the timestamp
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* counter as a source of real clock ticks to account for missed jiffies.
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*************************************************************************/
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static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* Clear Pending Interrupt by writing '1' to it */
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*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction ixp4xx_timer_irq = {
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.name = "timer1",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = ixp4xx_timer_interrupt,
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.dev_id = &clockevent_ixp4xx,
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};
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void __init ixp4xx_timer_init(void)
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{
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/* Reset/disable counter */
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*IXP4XX_OSRT1 = 0;
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/* Clear Pending Interrupt by writing '1' to it */
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*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
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/* Reset time-stamp counter */
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*IXP4XX_OSTS = 0;
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/* Connect the interrupt handler and enable the interrupt */
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setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
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ixp4xx_clocksource_init();
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ixp4xx_clockevent_init();
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}
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struct sys_timer ixp4xx_timer = {
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.init = ixp4xx_timer_init,
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};
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static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
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void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
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{
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memcpy(&ixp4xx_udc_info, info, sizeof *info);
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}
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static struct resource ixp4xx_udc_resources[] = {
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[0] = {
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.start = 0xc800b000,
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.end = 0xc800bfff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IXP4XX_USB,
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.end = IRQ_IXP4XX_USB,
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.flags = IORESOURCE_IRQ,
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},
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};
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/*
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* USB device controller. The IXP4xx uses the same controller as PXA25X,
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* so we just use the same device.
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*/
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static struct platform_device ixp4xx_udc_device = {
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.name = "pxa25x-udc",
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.id = -1,
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.num_resources = 2,
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.resource = ixp4xx_udc_resources,
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.dev = {
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.platform_data = &ixp4xx_udc_info,
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},
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};
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static struct platform_device *ixp4xx_devices[] __initdata = {
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&ixp4xx_udc_device,
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};
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static struct resource ixp46x_i2c_resources[] = {
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[0] = {
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.start = 0xc8011000,
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.end = 0xc801101c,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IXP4XX_I2C,
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.end = IRQ_IXP4XX_I2C,
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.flags = IORESOURCE_IRQ
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}
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};
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/*
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* I2C controller. The IXP46x uses the same block as the IOP3xx, so
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* we just use the same device name.
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*/
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static struct platform_device ixp46x_i2c_controller = {
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.name = "IOP3xx-I2C",
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.id = 0,
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.num_resources = 2,
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.resource = ixp46x_i2c_resources
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};
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static struct platform_device *ixp46x_devices[] __initdata = {
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&ixp46x_i2c_controller
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};
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unsigned long ixp4xx_exp_bus_size;
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EXPORT_SYMBOL(ixp4xx_exp_bus_size);
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static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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gpio_line_config(gpio, IXP4XX_GPIO_IN);
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return 0;
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}
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static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
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int level)
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{
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gpio_line_set(gpio, level);
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gpio_line_config(gpio, IXP4XX_GPIO_OUT);
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return 0;
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}
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static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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int value;
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gpio_line_get(gpio, &value);
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return value;
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}
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static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
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int value)
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{
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gpio_line_set(gpio, value);
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}
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static struct gpio_chip ixp4xx_gpio_chip = {
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.label = "IXP4XX_GPIO_CHIP",
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.direction_input = ixp4xx_gpio_direction_input,
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.direction_output = ixp4xx_gpio_direction_output,
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.get = ixp4xx_gpio_get_value,
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.set = ixp4xx_gpio_set_value,
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.to_irq = ixp4xx_gpio_to_irq,
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.base = 0,
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.ngpio = 16,
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};
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void __init ixp4xx_sys_init(void)
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{
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ixp4xx_exp_bus_size = SZ_16M;
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platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
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gpiochip_add(&ixp4xx_gpio_chip);
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if (cpu_is_ixp46x()) {
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int region;
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platform_add_devices(ixp46x_devices,
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ARRAY_SIZE(ixp46x_devices));
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for (region = 0; region < 7; region++) {
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if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
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ixp4xx_exp_bus_size = SZ_32M;
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break;
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}
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}
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}
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printk("IXP4xx: Using %luMiB expansion bus window size\n",
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ixp4xx_exp_bus_size >> 20);
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}
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/*
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* sched_clock()
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*/
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static u32 notrace ixp4xx_read_sched_clock(void)
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{
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return *IXP4XX_OSTS;
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}
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/*
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* clocksource
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*/
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static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
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{
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return *IXP4XX_OSTS;
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}
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unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
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EXPORT_SYMBOL(ixp4xx_timer_freq);
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static void __init ixp4xx_clocksource_init(void)
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{
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setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
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clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
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ixp4xx_clocksource_read);
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}
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/*
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* clockevents
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*/
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static int ixp4xx_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
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*IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
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return 0;
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}
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static void ixp4xx_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
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unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
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opts = IXP4XX_OST_ENABLE;
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set by 'set next_event' */
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osrt = 0;
|
|
opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
|
|
break;
|
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
|
opts &= ~IXP4XX_OST_ENABLE;
|
|
break;
|
|
case CLOCK_EVT_MODE_RESUME:
|
|
opts |= IXP4XX_OST_ENABLE;
|
|
break;
|
|
case CLOCK_EVT_MODE_UNUSED:
|
|
default:
|
|
osrt = opts = 0;
|
|
break;
|
|
}
|
|
|
|
*IXP4XX_OSRT1 = osrt | opts;
|
|
}
|
|
|
|
static struct clock_event_device clockevent_ixp4xx = {
|
|
.name = "ixp4xx timer1",
|
|
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
|
.rating = 200,
|
|
.shift = 24,
|
|
.set_mode = ixp4xx_set_mode,
|
|
.set_next_event = ixp4xx_set_next_event,
|
|
};
|
|
|
|
static void __init ixp4xx_clockevent_init(void)
|
|
{
|
|
clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
|
|
clockevent_ixp4xx.shift);
|
|
clockevent_ixp4xx.max_delta_ns =
|
|
clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
|
|
clockevent_ixp4xx.min_delta_ns =
|
|
clockevent_delta2ns(0xf, &clockevent_ixp4xx);
|
|
clockevent_ixp4xx.cpumask = cpumask_of(0);
|
|
|
|
clockevents_register_device(&clockevent_ixp4xx);
|
|
}
|
|
|
|
void ixp4xx_restart(char mode, const char *cmd)
|
|
{
|
|
if ( 1 && mode == 's') {
|
|
/* Jump into ROM at address 0 */
|
|
soft_restart(0);
|
|
} else {
|
|
/* Use on-chip reset capability */
|
|
|
|
/* set the "key" register to enable access to
|
|
* "timer" and "enable" registers
|
|
*/
|
|
*IXP4XX_OSWK = IXP4XX_WDT_KEY;
|
|
|
|
/* write 0 to the timer register for an immediate reset */
|
|
*IXP4XX_OSWT = 0;
|
|
|
|
*IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_IXP4XX_INDIRECT_PCI
|
|
/*
|
|
* In the case of using indirect PCI, we simply return the actual PCI
|
|
* address and our read/write implementation use that to drive the
|
|
* access registers. If something outside of PCI is ioremap'd, we
|
|
* fallback to the default.
|
|
*/
|
|
|
|
static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
|
|
unsigned int mtype, void *caller)
|
|
{
|
|
if (!is_pci_memory(addr))
|
|
return __arm_ioremap_caller(addr, size, mtype, caller);
|
|
|
|
return (void __iomem *)addr;
|
|
}
|
|
|
|
static void ixp4xx_iounmap(void __iomem *addr)
|
|
{
|
|
if (!is_pci_memory((__force u32)addr))
|
|
__iounmap(addr);
|
|
}
|
|
|
|
void __init ixp4xx_init_early(void)
|
|
{
|
|
arch_ioremap_caller = ixp4xx_ioremap_caller;
|
|
arch_iounmap = ixp4xx_iounmap;
|
|
}
|
|
#else
|
|
void __init ixp4xx_init_early(void) {}
|
|
#endif
|