forked from Minki/linux
3509c6fa05
Return the appropriate error code instead of hardcoding it. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
740 lines
21 KiB
C
740 lines
21 KiB
C
/*
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* GPIO driver for Marvell SoCs
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Andrew Lunn <andrew@lunn.ch>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This driver is a fairly straightforward GPIO driver for the
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* complete family of Marvell EBU SoC platforms (Orion, Dove,
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* Kirkwood, Discovery, Armada 370/XP). The only complexity of this
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* driver is the different register layout that exists between the
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* non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
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* platforms (MV78200 from the Discovery family and the Armada
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* XP). Therefore, this driver handles three variants of the GPIO
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* block:
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* - the basic variant, called "orion-gpio", with the simplest
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* register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
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* non-SMP Discovery systems
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* - the mv78200 variant for MV78200 Discovery systems. This variant
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* turns the edge mask and level mask registers into CPU0 edge
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* mask/level mask registers, and adds CPU1 edge mask/level mask
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* registers.
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* - the armadaxp variant for Armada XP systems. This variant keeps
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* the normal cause/edge mask/level mask registers when the global
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* interrupts are used, but adds per-CPU cause/edge mask/level mask
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* registers n a separate memory area for the per-CPU GPIO
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* interrupts.
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/of_irq.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/pinctrl/consumer.h>
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/*
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* GPIO unit register offsets.
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*/
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#define GPIO_OUT_OFF 0x0000
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#define GPIO_IO_CONF_OFF 0x0004
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#define GPIO_BLINK_EN_OFF 0x0008
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#define GPIO_IN_POL_OFF 0x000c
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#define GPIO_DATA_IN_OFF 0x0010
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#define GPIO_EDGE_CAUSE_OFF 0x0014
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#define GPIO_EDGE_MASK_OFF 0x0018
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#define GPIO_LEVEL_MASK_OFF 0x001c
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/* The MV78200 has per-CPU registers for edge mask and level mask */
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#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
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#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
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/* The Armada XP has per-CPU registers for interrupt cause, interrupt
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* mask and interrupt level mask. Those are relative to the
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* percpu_membase. */
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#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
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#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
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#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
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#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
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#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
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#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
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#define MVEBU_MAX_GPIO_PER_BANK 32
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struct mvebu_gpio_chip {
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struct gpio_chip chip;
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spinlock_t lock;
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void __iomem *membase;
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void __iomem *percpu_membase;
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int irqbase;
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struct irq_domain *domain;
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int soc_variant;
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};
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/*
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* Functions returning addresses of individual registers for a given
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* GPIO controller.
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*/
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static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_OUT_OFF;
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}
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static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_BLINK_EN_OFF;
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}
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static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_IO_CONF_OFF;
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}
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static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_IN_POL_OFF;
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}
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static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
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{
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return mvchip->membase + GPIO_DATA_IN_OFF;
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}
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static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
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{
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int cpu;
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switch (mvchip->soc_variant) {
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case MVEBU_GPIO_SOC_VARIANT_ORION:
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case MVEBU_GPIO_SOC_VARIANT_MV78200:
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return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
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default:
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BUG();
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}
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}
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static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
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{
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int cpu;
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switch (mvchip->soc_variant) {
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case MVEBU_GPIO_SOC_VARIANT_ORION:
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return mvchip->membase + GPIO_EDGE_MASK_OFF;
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case MVEBU_GPIO_SOC_VARIANT_MV78200:
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cpu = smp_processor_id();
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return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
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default:
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BUG();
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}
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}
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static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
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{
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int cpu;
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switch (mvchip->soc_variant) {
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case MVEBU_GPIO_SOC_VARIANT_ORION:
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return mvchip->membase + GPIO_LEVEL_MASK_OFF;
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case MVEBU_GPIO_SOC_VARIANT_MV78200:
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cpu = smp_processor_id();
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return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
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case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
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cpu = smp_processor_id();
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return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
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default:
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BUG();
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}
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}
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/*
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* Functions implementing the gpio_chip methods
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*/
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static int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
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{
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return pinctrl_request_gpio(chip->base + pin);
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}
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static void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
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{
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pinctrl_free_gpio(chip->base + pin);
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}
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static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
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{
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struct mvebu_gpio_chip *mvchip =
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container_of(chip, struct mvebu_gpio_chip, chip);
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unsigned long flags;
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u32 u;
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_out(mvchip));
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if (value)
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u |= 1 << pin;
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else
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u &= ~(1 << pin);
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writel_relaxed(u, mvebu_gpioreg_out(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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}
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static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
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{
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struct mvebu_gpio_chip *mvchip =
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container_of(chip, struct mvebu_gpio_chip, chip);
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u32 u;
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if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
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u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
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readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
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} else {
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u = readl_relaxed(mvebu_gpioreg_out(mvchip));
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}
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return (u >> pin) & 1;
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}
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static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value)
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{
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struct mvebu_gpio_chip *mvchip =
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container_of(chip, struct mvebu_gpio_chip, chip);
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unsigned long flags;
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u32 u;
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
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if (value)
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u |= 1 << pin;
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else
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u &= ~(1 << pin);
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writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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}
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static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
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{
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struct mvebu_gpio_chip *mvchip =
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container_of(chip, struct mvebu_gpio_chip, chip);
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unsigned long flags;
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int ret;
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u32 u;
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/* Check with the pinctrl driver whether this pin is usable as
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* an input GPIO */
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ret = pinctrl_gpio_direction_input(chip->base + pin);
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if (ret)
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return ret;
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
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u |= 1 << pin;
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writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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return 0;
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}
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static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
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int value)
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{
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struct mvebu_gpio_chip *mvchip =
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container_of(chip, struct mvebu_gpio_chip, chip);
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unsigned long flags;
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int ret;
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u32 u;
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/* Check with the pinctrl driver whether this pin is usable as
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* an output GPIO */
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ret = pinctrl_gpio_direction_output(chip->base + pin);
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if (ret)
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return ret;
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mvebu_gpio_blink(chip, pin, 0);
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mvebu_gpio_set(chip, pin, value);
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spin_lock_irqsave(&mvchip->lock, flags);
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u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
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u &= ~(1 << pin);
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writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
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spin_unlock_irqrestore(&mvchip->lock, flags);
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return 0;
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}
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static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
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{
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struct mvebu_gpio_chip *mvchip =
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container_of(chip, struct mvebu_gpio_chip, chip);
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return irq_create_mapping(mvchip->domain, pin);
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}
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/*
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* Functions implementing the irq_chip methods
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*/
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static void mvebu_gpio_irq_ack(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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u32 mask = ~(1 << (d->irq - gc->irq_base));
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irq_gc_lock(gc);
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writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
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irq_gc_unlock(gc);
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}
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static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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gc->mask_cache &= ~mask;
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writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
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irq_gc_unlock(gc);
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}
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static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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gc->mask_cache |= mask;
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writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
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irq_gc_unlock(gc);
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}
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static void mvebu_gpio_level_irq_mask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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gc->mask_cache &= ~mask;
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writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
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irq_gc_unlock(gc);
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}
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static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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u32 mask = 1 << (d->irq - gc->irq_base);
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irq_gc_lock(gc);
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gc->mask_cache |= mask;
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writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
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irq_gc_unlock(gc);
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}
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/*****************************************************************************
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* MVEBU GPIO IRQ
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*
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* GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
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* value of the line or the opposite value.
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*
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* Level IRQ handlers: DATA_IN is used directly as cause register.
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* Interrupt are masked by LEVEL_MASK registers.
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* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
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* Interrupt are masked by EDGE_MASK registers.
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* Both-edge handlers: Similar to regular Edge handlers, but also swaps
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* the polarity to catch the next line transaction.
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* This is a race condition that might not perfectly
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* work on some use cases.
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*
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* Every eight GPIO lines are grouped (OR'ed) before going up to main
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* cause register.
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*
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* EDGE cause mask
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* data-in /--------| |-----| |----\
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* -----| |----- ---- to main cause reg
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* X \----------------| |----/
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* polarity LEVEL mask
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*
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****************************************************************************/
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static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct mvebu_gpio_chip *mvchip = gc->private;
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int pin;
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u32 u;
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pin = d->hwirq;
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u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
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if (!u) {
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return -EINVAL;
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}
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type &= IRQ_TYPE_SENSE_MASK;
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if (type == IRQ_TYPE_NONE)
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return -EINVAL;
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/* Check if we need to change chip and handler */
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if (!(ct->type & type))
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if (irq_setup_alt_chip(d, type))
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return -EINVAL;
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/*
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* Configure interrupt polarity.
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*/
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
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u &= ~(1 << pin);
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writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
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break;
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
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u |= 1 << pin;
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writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
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break;
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case IRQ_TYPE_EDGE_BOTH: {
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u32 v;
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v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
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readl_relaxed(mvebu_gpioreg_data_in(mvchip));
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/*
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* set initial polarity based on current input level
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*/
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u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
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if (v & (1 << pin))
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u |= 1 << pin; /* falling */
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else
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u &= ~(1 << pin); /* rising */
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writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
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break;
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}
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}
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return 0;
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}
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static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
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u32 cause, type;
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int i;
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if (mvchip == NULL)
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return;
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cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
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readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
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cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
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readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
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for (i = 0; i < mvchip->chip.ngpio; i++) {
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int irq;
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irq = mvchip->irqbase + i;
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if (!(cause & (1 << i)))
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continue;
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type = irq_get_trigger_type(irq);
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if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
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/* Swap polarity (race with GPIO line) */
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u32 polarity;
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polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
|
|
polarity ^= 1 << i;
|
|
writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
|
|
}
|
|
generic_handle_irq(irq);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
#include <linux/seq_file.h>
|
|
|
|
static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
|
{
|
|
struct mvebu_gpio_chip *mvchip =
|
|
container_of(chip, struct mvebu_gpio_chip, chip);
|
|
u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
|
|
int i;
|
|
|
|
out = readl_relaxed(mvebu_gpioreg_out(mvchip));
|
|
io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
|
|
blink = readl_relaxed(mvebu_gpioreg_blink(mvchip));
|
|
in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
|
|
data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip));
|
|
cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip));
|
|
edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
|
|
lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
|
|
|
|
for (i = 0; i < chip->ngpio; i++) {
|
|
const char *label;
|
|
u32 msk;
|
|
bool is_out;
|
|
|
|
label = gpiochip_is_requested(chip, i);
|
|
if (!label)
|
|
continue;
|
|
|
|
msk = 1 << i;
|
|
is_out = !(io_conf & msk);
|
|
|
|
seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
|
|
|
|
if (is_out) {
|
|
seq_printf(s, " out %s %s\n",
|
|
out & msk ? "hi" : "lo",
|
|
blink & msk ? "(blink )" : "");
|
|
continue;
|
|
}
|
|
|
|
seq_printf(s, " in %s (act %s) - IRQ",
|
|
(data_in ^ in_pol) & msk ? "hi" : "lo",
|
|
in_pol & msk ? "lo" : "hi");
|
|
if (!((edg_msk | lvl_msk) & msk)) {
|
|
seq_printf(s, " disabled\n");
|
|
continue;
|
|
}
|
|
if (edg_msk & msk)
|
|
seq_printf(s, " edge ");
|
|
if (lvl_msk & msk)
|
|
seq_printf(s, " level");
|
|
seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
|
|
}
|
|
}
|
|
#else
|
|
#define mvebu_gpio_dbg_show NULL
|
|
#endif
|
|
|
|
static struct of_device_id mvebu_gpio_of_match[] = {
|
|
{
|
|
.compatible = "marvell,orion-gpio",
|
|
.data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
|
|
},
|
|
{
|
|
.compatible = "marvell,mv78200-gpio",
|
|
.data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
|
|
},
|
|
{
|
|
.compatible = "marvell,armadaxp-gpio",
|
|
.data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
|
|
},
|
|
{
|
|
/* sentinel */
|
|
},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
|
|
|
|
static int mvebu_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct mvebu_gpio_chip *mvchip;
|
|
const struct of_device_id *match;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct resource *res;
|
|
struct irq_chip_generic *gc;
|
|
struct irq_chip_type *ct;
|
|
struct clk *clk;
|
|
unsigned int ngpios;
|
|
int soc_variant;
|
|
int i, cpu, id;
|
|
|
|
match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
|
|
if (match)
|
|
soc_variant = (int) match->data;
|
|
else
|
|
soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
|
|
|
|
mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
|
|
if (!mvchip) {
|
|
dev_err(&pdev->dev, "Cannot allocate memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
|
|
dev_err(&pdev->dev, "Missing ngpios OF property\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
id = of_alias_get_id(pdev->dev.of_node, "gpio");
|
|
if (id < 0) {
|
|
dev_err(&pdev->dev, "Couldn't get OF id\n");
|
|
return id;
|
|
}
|
|
|
|
clk = devm_clk_get(&pdev->dev, NULL);
|
|
/* Not all SoCs require a clock.*/
|
|
if (!IS_ERR(clk))
|
|
clk_prepare_enable(clk);
|
|
|
|
mvchip->soc_variant = soc_variant;
|
|
mvchip->chip.label = dev_name(&pdev->dev);
|
|
mvchip->chip.dev = &pdev->dev;
|
|
mvchip->chip.request = mvebu_gpio_request;
|
|
mvchip->chip.free = mvebu_gpio_free;
|
|
mvchip->chip.direction_input = mvebu_gpio_direction_input;
|
|
mvchip->chip.get = mvebu_gpio_get;
|
|
mvchip->chip.direction_output = mvebu_gpio_direction_output;
|
|
mvchip->chip.set = mvebu_gpio_set;
|
|
mvchip->chip.to_irq = mvebu_gpio_to_irq;
|
|
mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
|
|
mvchip->chip.ngpio = ngpios;
|
|
mvchip->chip.can_sleep = false;
|
|
mvchip->chip.of_node = np;
|
|
mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
|
|
|
|
spin_lock_init(&mvchip->lock);
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
mvchip->membase = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(mvchip->membase))
|
|
return PTR_ERR(mvchip->membase);
|
|
|
|
/* The Armada XP has a second range of registers for the
|
|
* per-CPU registers */
|
|
if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
|
|
res);
|
|
if (IS_ERR(mvchip->percpu_membase))
|
|
return PTR_ERR(mvchip->percpu_membase);
|
|
}
|
|
|
|
/*
|
|
* Mask and clear GPIO interrupts.
|
|
*/
|
|
switch (soc_variant) {
|
|
case MVEBU_GPIO_SOC_VARIANT_ORION:
|
|
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
|
|
writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
|
|
writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
|
|
break;
|
|
case MVEBU_GPIO_SOC_VARIANT_MV78200:
|
|
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
|
|
for (cpu = 0; cpu < 2; cpu++) {
|
|
writel_relaxed(0, mvchip->membase +
|
|
GPIO_EDGE_MASK_MV78200_OFF(cpu));
|
|
writel_relaxed(0, mvchip->membase +
|
|
GPIO_LEVEL_MASK_MV78200_OFF(cpu));
|
|
}
|
|
break;
|
|
case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
|
|
writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
|
|
writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
|
|
writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
|
|
for (cpu = 0; cpu < 4; cpu++) {
|
|
writel_relaxed(0, mvchip->percpu_membase +
|
|
GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
|
|
writel_relaxed(0, mvchip->percpu_membase +
|
|
GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
|
|
writel_relaxed(0, mvchip->percpu_membase +
|
|
GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
|
|
}
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
gpiochip_add(&mvchip->chip);
|
|
|
|
/* Some gpio controllers do not provide irq support */
|
|
if (!of_irq_count(np))
|
|
return 0;
|
|
|
|
/* Setup the interrupt handlers. Each chip can have up to 4
|
|
* interrupt handlers, with each handler dealing with 8 GPIO
|
|
* pins. */
|
|
for (i = 0; i < 4; i++) {
|
|
int irq;
|
|
irq = platform_get_irq(pdev, i);
|
|
if (irq < 0)
|
|
continue;
|
|
irq_set_handler_data(irq, mvchip);
|
|
irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
|
|
}
|
|
|
|
mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
|
|
if (mvchip->irqbase < 0) {
|
|
dev_err(&pdev->dev, "no irqs\n");
|
|
return mvchip->irqbase;
|
|
}
|
|
|
|
gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
|
|
mvchip->membase, handle_level_irq);
|
|
if (!gc) {
|
|
dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
gc->private = mvchip;
|
|
ct = &gc->chip_types[0];
|
|
ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
|
|
ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
|
|
ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
|
|
ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
|
|
ct->chip.name = mvchip->chip.label;
|
|
|
|
ct = &gc->chip_types[1];
|
|
ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
|
|
ct->chip.irq_ack = mvebu_gpio_irq_ack;
|
|
ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
|
|
ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
|
|
ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
|
|
ct->handler = handle_edge_irq;
|
|
ct->chip.name = mvchip->chip.label;
|
|
|
|
irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
|
|
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
|
|
|
|
/* Setup irq domain on top of the generic chip. */
|
|
mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio,
|
|
mvchip->irqbase,
|
|
&irq_domain_simple_ops,
|
|
mvchip);
|
|
if (!mvchip->domain) {
|
|
dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
|
|
mvchip->chip.label);
|
|
irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
|
|
IRQ_LEVEL | IRQ_NOPROBE);
|
|
kfree(gc);
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver mvebu_gpio_driver = {
|
|
.driver = {
|
|
.name = "mvebu-gpio",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = mvebu_gpio_of_match,
|
|
},
|
|
.probe = mvebu_gpio_probe,
|
|
};
|
|
|
|
static int __init mvebu_gpio_init(void)
|
|
{
|
|
return platform_driver_register(&mvebu_gpio_driver);
|
|
}
|
|
postcore_initcall(mvebu_gpio_init);
|