forked from Minki/linux
cf09ee5997
Exynos4 MIPI phy registers are defined with macro calculating the offset for given phyN. Use the same method for Exynos5420 to be consistent. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
379 lines
11 KiB
C
379 lines
11 KiB
C
/*
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* Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
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*
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* Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
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* Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon/exynos5-pmu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/spinlock.h>
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#include <linux/soc/samsung/exynos-regs-pmu.h>
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#include <linux/mfd/syscon.h>
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enum exynos_mipi_phy_id {
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EXYNOS_MIPI_PHY_ID_NONE = -1,
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EXYNOS_MIPI_PHY_ID_CSIS0,
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EXYNOS_MIPI_PHY_ID_DSIM0,
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EXYNOS_MIPI_PHY_ID_CSIS1,
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EXYNOS_MIPI_PHY_ID_DSIM1,
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EXYNOS_MIPI_PHY_ID_CSIS2,
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EXYNOS_MIPI_PHYS_NUM
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};
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enum exynos_mipi_phy_regmap_id {
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EXYNOS_MIPI_REGMAP_PMU,
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EXYNOS_MIPI_REGMAP_DISP,
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EXYNOS_MIPI_REGMAP_CAM0,
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EXYNOS_MIPI_REGMAP_CAM1,
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EXYNOS_MIPI_REGMAPS_NUM
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};
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struct mipi_phy_device_desc {
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int num_phys;
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int num_regmaps;
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const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
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struct exynos_mipi_phy_desc {
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enum exynos_mipi_phy_id coupled_phy_id;
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u32 enable_val;
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unsigned int enable_reg;
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enum exynos_mipi_phy_regmap_id enable_map;
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u32 resetn_val;
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unsigned int resetn_reg;
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enum exynos_mipi_phy_regmap_id resetn_map;
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} phys[EXYNOS_MIPI_PHYS_NUM];
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};
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static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
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.num_regmaps = 1,
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.regmap_names = {"syscon"},
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.num_phys = 4,
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.phys = {
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{
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/* EXYNOS_MIPI_PHY_ID_CSIS0 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
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.enable_val = EXYNOS4_MIPI_PHY_ENABLE,
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.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
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.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_DSIM0 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
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.enable_val = EXYNOS4_MIPI_PHY_ENABLE,
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.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
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.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_CSIS1 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
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.enable_val = EXYNOS4_MIPI_PHY_ENABLE,
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.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
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.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_DSIM1 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
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.enable_val = EXYNOS4_MIPI_PHY_ENABLE,
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.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
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.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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},
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},
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};
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static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
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.num_regmaps = 1,
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.regmap_names = {"syscon"},
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.num_phys = 5,
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.phys = {
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{
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/* EXYNOS_MIPI_PHY_ID_CSIS0 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
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.enable_val = EXYNOS5_PHY_ENABLE,
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.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
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.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_DSIM0 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
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.enable_val = EXYNOS5_PHY_ENABLE,
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.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
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.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_CSIS1 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
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.enable_val = EXYNOS5_PHY_ENABLE,
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.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
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.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_DSIM1 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
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.enable_val = EXYNOS5_PHY_ENABLE,
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.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
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.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_CSIS2 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
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.enable_val = EXYNOS5_PHY_ENABLE,
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.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
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.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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},
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},
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};
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#define EXYNOS5433_SYSREG_DISP_MIPI_PHY 0x100C
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#define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON 0x1014
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#define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON 0x1020
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static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
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.num_regmaps = 4,
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.regmap_names = {
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"samsung,pmu-syscon",
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"samsung,disp-sysreg",
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"samsung,cam0-sysreg",
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"samsung,cam1-sysreg"
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},
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.num_phys = 5,
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.phys = {
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{
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/* EXYNOS_MIPI_PHY_ID_CSIS0 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
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.enable_val = EXYNOS5_PHY_ENABLE,
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.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = BIT(0),
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.resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
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.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
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}, {
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/* EXYNOS_MIPI_PHY_ID_DSIM0 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
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.enable_val = EXYNOS5_PHY_ENABLE,
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.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = BIT(0),
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.resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
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.resetn_map = EXYNOS_MIPI_REGMAP_DISP,
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}, {
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/* EXYNOS_MIPI_PHY_ID_CSIS1 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
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.enable_val = EXYNOS5_PHY_ENABLE,
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.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = BIT(1),
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.resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
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.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
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}, {
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/* EXYNOS_MIPI_PHY_ID_DSIM1 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
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.enable_val = EXYNOS5_PHY_ENABLE,
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.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = BIT(1),
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.resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
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.resetn_map = EXYNOS_MIPI_REGMAP_DISP,
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}, {
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/* EXYNOS_MIPI_PHY_ID_CSIS2 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
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.enable_val = EXYNOS5_PHY_ENABLE,
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.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(2),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = BIT(0),
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.resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
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.resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
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},
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},
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};
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struct exynos_mipi_video_phy {
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struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
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int num_phys;
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struct video_phy_desc {
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struct phy *phy;
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unsigned int index;
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const struct exynos_mipi_phy_desc *data;
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} phys[EXYNOS_MIPI_PHYS_NUM];
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spinlock_t slock;
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};
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static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
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struct exynos_mipi_video_phy *state, unsigned int on)
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{
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u32 val;
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spin_lock(&state->slock);
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/* disable in PMU sysreg */
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if (!on && data->coupled_phy_id >= 0 &&
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state->phys[data->coupled_phy_id].phy->power_count == 0) {
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regmap_read(state->regmaps[data->enable_map], data->enable_reg,
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&val);
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val &= ~data->enable_val;
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regmap_write(state->regmaps[data->enable_map], data->enable_reg,
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val);
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}
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/* PHY reset */
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regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
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val = on ? (val | data->resetn_val) : (val & ~data->resetn_val);
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regmap_write(state->regmaps[data->resetn_map], data->resetn_reg, val);
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/* enable in PMU sysreg */
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if (on) {
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regmap_read(state->regmaps[data->enable_map], data->enable_reg,
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&val);
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val |= data->enable_val;
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regmap_write(state->regmaps[data->enable_map], data->enable_reg,
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val);
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}
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spin_unlock(&state->slock);
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return 0;
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}
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#define to_mipi_video_phy(desc) \
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container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])
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static int exynos_mipi_video_phy_power_on(struct phy *phy)
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{
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struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
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struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
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return __set_phy_state(phy_desc->data, state, 1);
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}
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static int exynos_mipi_video_phy_power_off(struct phy *phy)
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{
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struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
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struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
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return __set_phy_state(phy_desc->data, state, 0);
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}
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static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
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if (WARN_ON(args->args[0] >= state->num_phys))
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return ERR_PTR(-ENODEV);
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return state->phys[args->args[0]].phy;
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}
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static const struct phy_ops exynos_mipi_video_phy_ops = {
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.power_on = exynos_mipi_video_phy_power_on,
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.power_off = exynos_mipi_video_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
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{
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const struct mipi_phy_device_desc *phy_dev;
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struct exynos_mipi_video_phy *state;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct phy_provider *phy_provider;
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unsigned int i;
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phy_dev = of_device_get_match_data(dev);
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if (!phy_dev)
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return -ENODEV;
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state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
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if (!state)
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return -ENOMEM;
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for (i = 0; i < phy_dev->num_regmaps; i++) {
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state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
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phy_dev->regmap_names[i]);
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if (IS_ERR(state->regmaps[i]))
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return PTR_ERR(state->regmaps[i]);
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}
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state->num_phys = phy_dev->num_phys;
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spin_lock_init(&state->slock);
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dev_set_drvdata(dev, state);
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for (i = 0; i < state->num_phys; i++) {
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struct phy *phy = devm_phy_create(dev, NULL,
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&exynos_mipi_video_phy_ops);
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if (IS_ERR(phy)) {
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dev_err(dev, "failed to create PHY %d\n", i);
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return PTR_ERR(phy);
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}
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state->phys[i].phy = phy;
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state->phys[i].index = i;
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state->phys[i].data = &phy_dev->phys[i];
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phy_set_drvdata(phy, &state->phys[i]);
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}
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phy_provider = devm_of_phy_provider_register(dev,
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exynos_mipi_video_phy_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
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{
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.compatible = "samsung,s5pv210-mipi-video-phy",
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.data = &s5pv210_mipi_phy,
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}, {
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.compatible = "samsung,exynos5420-mipi-video-phy",
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.data = &exynos5420_mipi_phy,
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}, {
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.compatible = "samsung,exynos5433-mipi-video-phy",
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.data = &exynos5433_mipi_phy,
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
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static struct platform_driver exynos_mipi_video_phy_driver = {
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.probe = exynos_mipi_video_phy_probe,
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.driver = {
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.of_match_table = exynos_mipi_video_phy_of_match,
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.name = "exynos-mipi-video-phy",
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}
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};
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module_platform_driver(exynos_mipi_video_phy_driver);
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MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
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MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
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MODULE_LICENSE("GPL v2");
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