forked from Minki/linux
33d3bc9556
The LPI pending status for a GICv3 redistributor is held in a table in (guest) memory. To achieve reasonable performance, we cache the pending bit in our struct vgic_irq. The initial pending state must be read from guest memory upon enabling LPIs for this redistributor. As we can't access the guest memory while we hold the lpi_list spinlock, we create a snapshot of the LPI list and iterate over that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
710 lines
18 KiB
C
710 lines
18 KiB
C
/*
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* GICv3 ITS emulation
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*
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* Copyright (C) 2015,2016 ARM Ltd.
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* Author: Andre Przywara <andre.przywara@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/cpu.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/uaccess.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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struct its_device {
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struct list_head dev_list;
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/* the head for the list of ITTEs */
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struct list_head itt_head;
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u32 device_id;
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};
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#define COLLECTION_NOT_MAPPED ((u32)~0)
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struct its_collection {
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struct list_head coll_list;
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u32 collection_id;
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u32 target_addr;
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};
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#define its_is_collection_mapped(coll) ((coll) && \
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((coll)->target_addr != COLLECTION_NOT_MAPPED))
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struct its_itte {
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struct list_head itte_list;
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struct vgic_irq *irq;
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struct its_collection *collection;
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u32 lpi;
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u32 event_id;
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};
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/*
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* We only implement 48 bits of PA at the moment, although the ITS
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* supports more. Let's be restrictive here.
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*/
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#define CBASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 12))
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#define PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(47, 16))
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/*
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* Create a snapshot of the current LPI list, so that we can enumerate all
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* LPIs without holding any lock.
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* Returns the array length and puts the kmalloc'ed array into intid_ptr.
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*/
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static int vgic_copy_lpi_list(struct kvm *kvm, u32 **intid_ptr)
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{
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struct vgic_dist *dist = &kvm->arch.vgic;
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struct vgic_irq *irq;
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u32 *intids;
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int irq_count = dist->lpi_list_count, i = 0;
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/*
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* We use the current value of the list length, which may change
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* after the kmalloc. We don't care, because the guest shouldn't
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* change anything while the command handling is still running,
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* and in the worst case we would miss a new IRQ, which one wouldn't
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* expect to be covered by this command anyway.
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*/
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intids = kmalloc_array(irq_count, sizeof(intids[0]), GFP_KERNEL);
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if (!intids)
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return -ENOMEM;
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spin_lock(&dist->lpi_list_lock);
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list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
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/* We don't need to "get" the IRQ, as we hold the list lock. */
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intids[i] = irq->intid;
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if (++i == irq_count)
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break;
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}
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spin_unlock(&dist->lpi_list_lock);
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*intid_ptr = intids;
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return irq_count;
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}
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/*
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* Scan the whole LPI pending table and sync the pending bit in there
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* with our own data structures. This relies on the LPI being
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* mapped before.
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*/
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static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
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{
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gpa_t pendbase = PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
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struct vgic_irq *irq;
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int last_byte_offset = -1;
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int ret = 0;
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u32 *intids;
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int nr_irqs, i;
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nr_irqs = vgic_copy_lpi_list(vcpu->kvm, &intids);
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if (nr_irqs < 0)
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return nr_irqs;
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for (i = 0; i < nr_irqs; i++) {
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int byte_offset, bit_nr;
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u8 pendmask;
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byte_offset = intids[i] / BITS_PER_BYTE;
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bit_nr = intids[i] % BITS_PER_BYTE;
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/*
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* For contiguously allocated LPIs chances are we just read
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* this very same byte in the last iteration. Reuse that.
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*/
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if (byte_offset != last_byte_offset) {
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ret = kvm_read_guest(vcpu->kvm, pendbase + byte_offset,
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&pendmask, 1);
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if (ret) {
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kfree(intids);
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return ret;
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}
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last_byte_offset = byte_offset;
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}
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irq = vgic_get_irq(vcpu->kvm, NULL, intids[i]);
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spin_lock(&irq->irq_lock);
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irq->pending = pendmask & (1U << bit_nr);
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vgic_queue_irq_unlock(vcpu->kvm, irq);
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vgic_put_irq(vcpu->kvm, irq);
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}
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kfree(intids);
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return ret;
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}
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static unsigned long vgic_mmio_read_its_ctlr(struct kvm *vcpu,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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u32 reg = 0;
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mutex_lock(&its->cmd_lock);
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if (its->creadr == its->cwriter)
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reg |= GITS_CTLR_QUIESCENT;
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if (its->enabled)
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reg |= GITS_CTLR_ENABLE;
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mutex_unlock(&its->cmd_lock);
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return reg;
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}
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static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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its->enabled = !!(val & GITS_CTLR_ENABLE);
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}
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static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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u64 reg = GITS_TYPER_PLPIS;
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/*
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* We use linear CPU numbers for redistributor addressing,
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* so GITS_TYPER.PTA is 0.
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* Also we force all PROPBASER registers to be the same, so
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* CommonLPIAff is 0 as well.
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* To avoid memory waste in the guest, we keep the number of IDBits and
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* DevBits low - as least for the time being.
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*/
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reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT;
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reg |= 0x0f << GITS_TYPER_IDBITS_SHIFT;
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return extract_bytes(reg, addr & 7, len);
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}
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static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
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}
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static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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switch (addr & 0xffff) {
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case GITS_PIDR0:
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return 0x92; /* part number, bits[7:0] */
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case GITS_PIDR1:
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return 0xb4; /* part number, bits[11:8] */
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case GITS_PIDR2:
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return GIC_PIDR2_ARCH_GICv3 | 0x0b;
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case GITS_PIDR4:
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return 0x40; /* This is a 64K software visible page */
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/* The following are the ID registers for (any) GIC. */
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case GITS_CIDR0:
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return 0x0d;
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case GITS_CIDR1:
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return 0xf0;
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case GITS_CIDR2:
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return 0x05;
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case GITS_CIDR3:
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return 0xb1;
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}
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return 0;
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}
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/* Requires the its_lock to be held. */
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static void its_free_itte(struct kvm *kvm, struct its_itte *itte)
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{
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list_del(&itte->itte_list);
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/* This put matches the get in vgic_add_lpi. */
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vgic_put_irq(kvm, itte->irq);
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kfree(itte);
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}
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static int vgic_its_handle_command(struct kvm *kvm, struct vgic_its *its,
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u64 *its_cmd)
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{
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return -ENODEV;
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}
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static u64 vgic_sanitise_its_baser(u64 reg)
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{
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reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK,
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GITS_BASER_SHAREABILITY_SHIFT,
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vgic_sanitise_shareability);
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reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK,
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GITS_BASER_INNER_CACHEABILITY_SHIFT,
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vgic_sanitise_inner_cacheability);
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reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK,
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GITS_BASER_OUTER_CACHEABILITY_SHIFT,
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vgic_sanitise_outer_cacheability);
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/* Bits 15:12 contain bits 51:48 of the PA, which we don't support. */
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reg &= ~GENMASK_ULL(15, 12);
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/* We support only one (ITS) page size: 64K */
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reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K;
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return reg;
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}
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static u64 vgic_sanitise_its_cbaser(u64 reg)
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{
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reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK,
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GITS_CBASER_SHAREABILITY_SHIFT,
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vgic_sanitise_shareability);
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reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK,
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GITS_CBASER_INNER_CACHEABILITY_SHIFT,
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vgic_sanitise_inner_cacheability);
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reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK,
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GITS_CBASER_OUTER_CACHEABILITY_SHIFT,
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vgic_sanitise_outer_cacheability);
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/*
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* Sanitise the physical address to be 64k aligned.
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* Also limit the physical addresses to 48 bits.
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*/
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reg &= ~(GENMASK_ULL(51, 48) | GENMASK_ULL(15, 12));
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return reg;
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}
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static unsigned long vgic_mmio_read_its_cbaser(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return extract_bytes(its->cbaser, addr & 7, len);
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}
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static void vgic_mmio_write_its_cbaser(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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/* When GITS_CTLR.Enable is 1, this register is RO. */
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if (its->enabled)
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return;
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mutex_lock(&its->cmd_lock);
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its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val);
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its->cbaser = vgic_sanitise_its_cbaser(its->cbaser);
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its->creadr = 0;
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/*
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* CWRITER is architecturally UNKNOWN on reset, but we need to reset
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* it to CREADR to make sure we start with an empty command buffer.
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*/
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its->cwriter = its->creadr;
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mutex_unlock(&its->cmd_lock);
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}
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#define ITS_CMD_BUFFER_SIZE(baser) ((((baser) & 0xff) + 1) << 12)
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#define ITS_CMD_SIZE 32
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#define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5))
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/*
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* By writing to CWRITER the guest announces new commands to be processed.
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* To avoid any races in the first place, we take the its_cmd lock, which
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* protects our ring buffer variables, so that there is only one user
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* per ITS handling commands at a given time.
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*/
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static void vgic_mmio_write_its_cwriter(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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gpa_t cbaser;
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u64 cmd_buf[4];
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u32 reg;
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if (!its)
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return;
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mutex_lock(&its->cmd_lock);
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reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
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reg = ITS_CMD_OFFSET(reg);
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if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
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mutex_unlock(&its->cmd_lock);
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return;
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}
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its->cwriter = reg;
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cbaser = CBASER_ADDRESS(its->cbaser);
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while (its->cwriter != its->creadr) {
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int ret = kvm_read_guest(kvm, cbaser + its->creadr,
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cmd_buf, ITS_CMD_SIZE);
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/*
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* If kvm_read_guest() fails, this could be due to the guest
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* programming a bogus value in CBASER or something else going
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* wrong from which we cannot easily recover.
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* According to section 6.3.2 in the GICv3 spec we can just
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* ignore that command then.
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*/
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if (!ret)
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vgic_its_handle_command(kvm, its, cmd_buf);
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its->creadr += ITS_CMD_SIZE;
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if (its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser))
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its->creadr = 0;
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}
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mutex_unlock(&its->cmd_lock);
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}
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static unsigned long vgic_mmio_read_its_cwriter(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return extract_bytes(its->cwriter, addr & 0x7, len);
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}
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static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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return extract_bytes(its->creadr, addr & 0x7, len);
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}
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#define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
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static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len)
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{
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u64 reg;
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switch (BASER_INDEX(addr)) {
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case 0:
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reg = its->baser_device_table;
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break;
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case 1:
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reg = its->baser_coll_table;
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break;
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default:
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reg = 0;
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break;
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}
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return extract_bytes(reg, addr & 7, len);
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}
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#define GITS_BASER_RO_MASK (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))
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static void vgic_mmio_write_its_baser(struct kvm *kvm,
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struct vgic_its *its,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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u64 entry_size, device_type;
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u64 reg, *regptr, clearbits = 0;
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/* When GITS_CTLR.Enable is 1, we ignore write accesses. */
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if (its->enabled)
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return;
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switch (BASER_INDEX(addr)) {
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case 0:
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regptr = &its->baser_device_table;
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entry_size = 8;
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device_type = GITS_BASER_TYPE_DEVICE;
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break;
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case 1:
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regptr = &its->baser_coll_table;
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entry_size = 8;
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device_type = GITS_BASER_TYPE_COLLECTION;
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clearbits = GITS_BASER_INDIRECT;
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break;
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default:
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return;
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}
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reg = update_64bit_reg(*regptr, addr & 7, len, val);
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reg &= ~GITS_BASER_RO_MASK;
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reg &= ~clearbits;
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reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
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reg |= device_type << GITS_BASER_TYPE_SHIFT;
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reg = vgic_sanitise_its_baser(reg);
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*regptr = reg;
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}
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#define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
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{ \
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.reg_offset = off, \
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.len = length, \
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.access_flags = acc, \
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.its_read = rd, \
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.its_write = wr, \
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}
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static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
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gpa_t addr, unsigned int len, unsigned long val)
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{
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/* Ignore */
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}
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static struct vgic_register_region its_registers[] = {
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REGISTER_ITS_DESC(GITS_CTLR,
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vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
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VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_IIDR,
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vgic_mmio_read_its_iidr, its_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_TYPER,
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vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CBASER,
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vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_ITS_DESC(GITS_CWRITER,
|
|
vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
|
|
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
|
|
REGISTER_ITS_DESC(GITS_CREADR,
|
|
vgic_mmio_read_its_creadr, its_mmio_write_wi, 8,
|
|
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
|
|
REGISTER_ITS_DESC(GITS_BASER,
|
|
vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
|
|
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
|
|
REGISTER_ITS_DESC(GITS_IDREGS_BASE,
|
|
vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
|
|
VGIC_ACCESS_32bit),
|
|
};
|
|
|
|
/* This is called on setting the LPI enable bit in the redistributor. */
|
|
void vgic_enable_lpis(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (!(vcpu->arch.vgic_cpu.pendbaser & GICR_PENDBASER_PTZ))
|
|
its_sync_lpi_pending_table(vcpu);
|
|
}
|
|
|
|
static int vgic_its_init_its(struct kvm *kvm, struct vgic_its *its)
|
|
{
|
|
struct vgic_io_device *iodev = &its->iodev;
|
|
int ret;
|
|
|
|
if (its->initialized)
|
|
return 0;
|
|
|
|
if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base))
|
|
return -ENXIO;
|
|
|
|
iodev->regions = its_registers;
|
|
iodev->nr_regions = ARRAY_SIZE(its_registers);
|
|
kvm_iodevice_init(&iodev->dev, &kvm_io_gic_ops);
|
|
|
|
iodev->base_addr = its->vgic_its_base;
|
|
iodev->iodev_type = IODEV_ITS;
|
|
iodev->its = its;
|
|
mutex_lock(&kvm->slots_lock);
|
|
ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, iodev->base_addr,
|
|
KVM_VGIC_V3_ITS_SIZE, &iodev->dev);
|
|
mutex_unlock(&kvm->slots_lock);
|
|
|
|
if (!ret)
|
|
its->initialized = true;
|
|
|
|
return ret;
|
|
}
|
|
|
|
#define INITIAL_BASER_VALUE \
|
|
(GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) | \
|
|
GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner) | \
|
|
GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | \
|
|
((8ULL - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | \
|
|
GITS_BASER_PAGE_SIZE_64K)
|
|
|
|
#define INITIAL_PROPBASER_VALUE \
|
|
(GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) | \
|
|
GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner) | \
|
|
GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable))
|
|
|
|
static int vgic_its_create(struct kvm_device *dev, u32 type)
|
|
{
|
|
struct vgic_its *its;
|
|
|
|
if (type != KVM_DEV_TYPE_ARM_VGIC_ITS)
|
|
return -ENODEV;
|
|
|
|
its = kzalloc(sizeof(struct vgic_its), GFP_KERNEL);
|
|
if (!its)
|
|
return -ENOMEM;
|
|
|
|
mutex_init(&its->its_lock);
|
|
mutex_init(&its->cmd_lock);
|
|
|
|
its->vgic_its_base = VGIC_ADDR_UNDEF;
|
|
|
|
INIT_LIST_HEAD(&its->device_list);
|
|
INIT_LIST_HEAD(&its->collection_list);
|
|
|
|
dev->kvm->arch.vgic.has_its = true;
|
|
its->initialized = false;
|
|
its->enabled = false;
|
|
|
|
its->baser_device_table = INITIAL_BASER_VALUE |
|
|
((u64)GITS_BASER_TYPE_DEVICE << GITS_BASER_TYPE_SHIFT);
|
|
its->baser_coll_table = INITIAL_BASER_VALUE |
|
|
((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
|
|
dev->kvm->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
|
|
|
|
dev->private = its;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void vgic_its_destroy(struct kvm_device *kvm_dev)
|
|
{
|
|
struct kvm *kvm = kvm_dev->kvm;
|
|
struct vgic_its *its = kvm_dev->private;
|
|
struct its_device *dev;
|
|
struct its_itte *itte;
|
|
struct list_head *dev_cur, *dev_temp;
|
|
struct list_head *cur, *temp;
|
|
|
|
/*
|
|
* We may end up here without the lists ever having been initialized.
|
|
* Check this and bail out early to avoid dereferencing a NULL pointer.
|
|
*/
|
|
if (!its->device_list.next)
|
|
return;
|
|
|
|
mutex_lock(&its->its_lock);
|
|
list_for_each_safe(dev_cur, dev_temp, &its->device_list) {
|
|
dev = container_of(dev_cur, struct its_device, dev_list);
|
|
list_for_each_safe(cur, temp, &dev->itt_head) {
|
|
itte = (container_of(cur, struct its_itte, itte_list));
|
|
its_free_itte(kvm, itte);
|
|
}
|
|
list_del(dev_cur);
|
|
kfree(dev);
|
|
}
|
|
|
|
list_for_each_safe(cur, temp, &its->collection_list) {
|
|
list_del(cur);
|
|
kfree(container_of(cur, struct its_collection, coll_list));
|
|
}
|
|
mutex_unlock(&its->its_lock);
|
|
|
|
kfree(its);
|
|
}
|
|
|
|
static int vgic_its_has_attr(struct kvm_device *dev,
|
|
struct kvm_device_attr *attr)
|
|
{
|
|
switch (attr->group) {
|
|
case KVM_DEV_ARM_VGIC_GRP_ADDR:
|
|
switch (attr->attr) {
|
|
case KVM_VGIC_ITS_ADDR_TYPE:
|
|
return 0;
|
|
}
|
|
break;
|
|
case KVM_DEV_ARM_VGIC_GRP_CTRL:
|
|
switch (attr->attr) {
|
|
case KVM_DEV_ARM_VGIC_CTRL_INIT:
|
|
return 0;
|
|
}
|
|
break;
|
|
}
|
|
return -ENXIO;
|
|
}
|
|
|
|
static int vgic_its_set_attr(struct kvm_device *dev,
|
|
struct kvm_device_attr *attr)
|
|
{
|
|
struct vgic_its *its = dev->private;
|
|
int ret;
|
|
|
|
switch (attr->group) {
|
|
case KVM_DEV_ARM_VGIC_GRP_ADDR: {
|
|
u64 __user *uaddr = (u64 __user *)(long)attr->addr;
|
|
unsigned long type = (unsigned long)attr->attr;
|
|
u64 addr;
|
|
|
|
if (type != KVM_VGIC_ITS_ADDR_TYPE)
|
|
return -ENODEV;
|
|
|
|
if (its->initialized)
|
|
return -EBUSY;
|
|
|
|
if (copy_from_user(&addr, uaddr, sizeof(addr)))
|
|
return -EFAULT;
|
|
|
|
ret = vgic_check_ioaddr(dev->kvm, &its->vgic_its_base,
|
|
addr, SZ_64K);
|
|
if (ret)
|
|
return ret;
|
|
|
|
its->vgic_its_base = addr;
|
|
|
|
return 0;
|
|
}
|
|
case KVM_DEV_ARM_VGIC_GRP_CTRL:
|
|
switch (attr->attr) {
|
|
case KVM_DEV_ARM_VGIC_CTRL_INIT:
|
|
return vgic_its_init_its(dev->kvm, its);
|
|
}
|
|
break;
|
|
}
|
|
return -ENXIO;
|
|
}
|
|
|
|
static int vgic_its_get_attr(struct kvm_device *dev,
|
|
struct kvm_device_attr *attr)
|
|
{
|
|
switch (attr->group) {
|
|
case KVM_DEV_ARM_VGIC_GRP_ADDR: {
|
|
struct vgic_its *its = dev->private;
|
|
u64 addr = its->vgic_its_base;
|
|
u64 __user *uaddr = (u64 __user *)(long)attr->addr;
|
|
unsigned long type = (unsigned long)attr->attr;
|
|
|
|
if (type != KVM_VGIC_ITS_ADDR_TYPE)
|
|
return -ENODEV;
|
|
|
|
if (copy_to_user(uaddr, &addr, sizeof(addr)))
|
|
return -EFAULT;
|
|
break;
|
|
default:
|
|
return -ENXIO;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct kvm_device_ops kvm_arm_vgic_its_ops = {
|
|
.name = "kvm-arm-vgic-its",
|
|
.create = vgic_its_create,
|
|
.destroy = vgic_its_destroy,
|
|
.set_attr = vgic_its_set_attr,
|
|
.get_attr = vgic_its_get_attr,
|
|
.has_attr = vgic_its_has_attr,
|
|
};
|
|
|
|
int kvm_vgic_register_its_device(void)
|
|
{
|
|
return kvm_register_device_ops(&kvm_arm_vgic_its_ops,
|
|
KVM_DEV_TYPE_ARM_VGIC_ITS);
|
|
}
|