forked from Minki/linux
2ccdd1e77d
We are currently using the ARMv6 operations but need to duplicate some of the code because of the introduction of the new CPU barrier instructions in ARMv7. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
263 lines
6.2 KiB
ArmAsm
263 lines
6.2 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-v7.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv7 processor support.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/elf.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#define TTB_C (1 << 0)
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#define TTB_S (1 << 1)
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#define TTB_RGN_OC_WT (2 << 3)
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#define TTB_RGN_OC_WB (3 << 3)
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ENTRY(cpu_v7_proc_init)
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mov pc, lr
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ENTRY(cpu_v7_proc_fin)
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mov pc, lr
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/*
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* cpu_v7_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*
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* It is assumed that:
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*/
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.align 5
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ENTRY(cpu_v7_reset)
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mov pc, r0
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/*
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* cpu_v7_do_idle()
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*
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* Idle the processor (eg, wait for interrupt).
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*
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v7_do_idle)
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.long 0xe320f003 @ ARM V7 WFI instruction
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mov pc, lr
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ENTRY(cpu_v7_dcache_clean_area)
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#ifndef TLB_CAN_READ_FROM_L1_CACHE
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dcache_line_size r2, r3
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, r2
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subs r1, r1, r2
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bhi 1b
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dsb
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#endif
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mov pc, lr
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/*
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* cpu_v7_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys
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*
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* - pgd_phys - physical address of new TTB
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*
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* It is assumed that:
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* - we are not using split page tables
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*/
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ENTRY(cpu_v7_switch_mm)
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
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mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
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isb
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1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
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isb
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mcr p15, 0, r1, c13, c0, 1 @ set context ID
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isb
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mov pc, lr
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/*
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* cpu_v7_set_pte_ext(ptep, pte)
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*
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* Set a level 2 translation table entry.
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*
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* - ptep - pointer to level 2 translation table entry
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* (hardware version is stored at -1024 bytes)
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* - pte - PTE value to store
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* - ext - value for extended PTE bits
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*
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* Permissions:
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* YUWD APX AP1 AP0 SVC User
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* 0xxx 0 0 0 no acc no acc
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* 100x 1 0 1 r/o no acc
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* 10x0 1 0 1 r/o no acc
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* 1011 0 0 1 r/w no acc
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* 110x 0 1 0 r/w r/o
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* 11x0 0 1 0 r/w r/o
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* 1111 0 1 1 r/w r/w
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*/
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ENTRY(cpu_v7_set_pte_ext)
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str r1, [r0], #-2048 @ linux version
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bic r3, r1, #0x000003f0
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bic r3, r3, #0x00000003
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orr r3, r3, r2
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orr r3, r3, #PTE_EXT_AP0 | 2
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tst r1, #L_PTE_WRITE
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tstne r1, #L_PTE_DIRTY
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orreq r3, r3, #PTE_EXT_APX
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tst r1, #L_PTE_USER
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orrne r3, r3, #PTE_EXT_AP1
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tstne r3, #PTE_EXT_APX
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bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
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tst r1, #L_PTE_YOUNG
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biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
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tst r1, #L_PTE_EXEC
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orreq r3, r3, #PTE_EXT_XN
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tst r1, #L_PTE_PRESENT
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moveq r3, #0
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str r3, [r0]
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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mov pc, lr
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cpu_v7_name:
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.ascii "ARMv7 Processor"
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.align
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.section ".text.init", #alloc, #execinstr
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/*
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* __v7_setup
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*
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* on. Return in r0 the new CP15 C1 control register setting.
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*
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* We automatically detect if we have a Harvard cache, and use the
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* Harvard cache control instructions insead of the unified cache
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* control instructions.
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*
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* This should be able to cover all ARMv7 cores.
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*
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* It is assumed that:
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* - cache type register is implemented
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*/
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__v7_setup:
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adr r12, __v7_setup_stack @ the local stack
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stmia r12, {r0-r5, r7, r9, r11, lr}
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bl v7_flush_dcache_all
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ldmia r12, {r0-r5, r7, r9, r11, lr}
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mov r10, #0
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#ifdef HARVARD_CACHE
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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#endif
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dsb
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r10, c2, c0, 2 @ TTB control register
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orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
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mcr p15, 0, r4, c2, c0, 0 @ load TTB0
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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mov r10, #0x1f @ domains 0, 1 = manager
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mcr p15, 0, r10, c3, c0, 0 @ load domain access register
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#ifndef CONFIG_CPU_L2CACHE_DISABLE
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@ L2 cache configuration in the L2 aux control register
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mrc p15, 1, r10, c9, c0, 2
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bic r10, r10, #(1 << 16) @ L2 outer cache
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mcr p15, 1, r10, c9, c0, 2
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@ L2 cache is enabled in the aux control register
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mrc p15, 0, r10, c1, c0, 1
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orr r10, r10, #2
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mcr p15, 0, r10, c1, c0, 1
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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ldr r10, cr1_clear @ get mask for bits to clear
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bic r0, r0, r10 @ clear bits them
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ldr r10, cr1_set @ get mask for bits to set
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orr r0, r0, r10 @ set them
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mov pc, lr @ return to head.S:__ret
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/*
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* V X F I D LR
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* .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
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* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
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* 0 110 0011 1.00 .111 1101 < we want
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*/
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.type cr1_clear, #object
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.type cr1_set, #object
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cr1_clear:
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.word 0x0120c302
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cr1_set:
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.word 0x00c0387d
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__v7_setup_stack:
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.space 4 * 11 @ 11 registers
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.type v7_processor_functions, #object
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ENTRY(v7_processor_functions)
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.word v7_early_abort
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.word cpu_v7_proc_init
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.word cpu_v7_proc_fin
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.word cpu_v7_reset
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.word cpu_v7_do_idle
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.word cpu_v7_dcache_clean_area
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.word cpu_v7_switch_mm
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.word cpu_v7_set_pte_ext
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.size v7_processor_functions, . - v7_processor_functions
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.type cpu_arch_name, #object
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cpu_arch_name:
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.asciz "armv7"
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.size cpu_arch_name, . - cpu_arch_name
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.type cpu_elf_name, #object
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cpu_elf_name:
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.asciz "v7"
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.size cpu_elf_name, . - cpu_elf_name
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.align
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.section ".proc.info.init", #alloc, #execinstr
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/*
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* Match any ARMv7 processor core.
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*/
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.type __v7_proc_info, #object
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__v7_proc_info:
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.long 0x000f0000 @ Required ID value
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.long 0x000f0000 @ Mask for ID
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_SECT_XN | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __v7_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
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.long cpu_v7_name
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.long v7_processor_functions
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.long v7wbi_tlb_fns
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.long v6_user_fns
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.long v7_cache_fns
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.size __v7_proc_info, . - __v7_proc_info
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