forked from Minki/linux
3393d42205
An earlier patch updated the Tegra DT bindings to require resets and reset-names properties to be filled in. This patch updates the DT files to include those properties. Note that any legacy clocks and clock-names entries that are replaced by reset properties are not yet removed; the drivers must be updated to use the new resets and reset-names properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com>
612 lines
17 KiB
Plaintext
612 lines
17 KiB
Plaintext
#include <dt-bindings/clock/tegra114-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra114";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uarta;
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serial1 = &uartb;
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serial2 = &uartc;
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serial3 = &uartd;
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};
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gic: interrupt-controller {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x50041000 0x1000>,
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<0x50042000 0x1000>,
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<0x50044000 0x2000>,
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<0x50046000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_TIMER>;
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};
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tegra_car: clock {
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compatible = "nvidia,tegra114-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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apbdma: dma {
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compatible = "nvidia,tegra114-apbdma";
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reg = <0x6000a000 0x1400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
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resets = <&tegra_car 34>;
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reset-names = "dma";
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};
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ahb: ahb {
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compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
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reg = <0x6000c004 0x14c>;
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};
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gpio: gpio {
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compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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pinmux: pinmux {
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compatible = "nvidia,tegra114-pinmux";
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reg = <0x70000868 0x148 /* Pad control registers */
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0x70003000 0x40c>; /* Mux registers */
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};
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
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* the APB DMA based serial driver, the comptible is
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* "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
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*/
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uarta: serial@70006000 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 8>;
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clocks = <&tegra_car TEGRA114_CLK_UARTA>;
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resets = <&tegra_car 6>;
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reset-names = "serial";
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status = "disabled";
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};
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uartb: serial@70006040 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 9>;
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clocks = <&tegra_car TEGRA114_CLK_UARTB>;
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resets = <&tegra_car 7>;
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reset-names = "serial";
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status = "disabled";
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};
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uartc: serial@70006200 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 10>;
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clocks = <&tegra_car TEGRA114_CLK_UARTC>;
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resets = <&tegra_car 55>;
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reset-names = "serial";
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status = "disabled";
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};
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uartd: serial@70006300 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 19>;
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clocks = <&tegra_car TEGRA114_CLK_UARTD>;
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resets = <&tegra_car 65>;
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reset-names = "serial";
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status = "disabled";
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};
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pwm: pwm {
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compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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clocks = <&tegra_car TEGRA114_CLK_PWM>;
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resets = <&tegra_car 17>;
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reset-names = "pwm";
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status = "disabled";
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};
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i2c@7000c000 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_I2C1>;
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clock-names = "div-clk";
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resets = <&tegra_car 12>;
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reset-names = "i2c";
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status = "disabled";
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};
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i2c@7000c400 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c400 0x100>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_I2C2>;
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clock-names = "div-clk";
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resets = <&tegra_car 54>;
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reset-names = "i2c";
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status = "disabled";
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};
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i2c@7000c500 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c500 0x100>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_I2C3>;
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clock-names = "div-clk";
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resets = <&tegra_car 67>;
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reset-names = "i2c";
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status = "disabled";
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};
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i2c@7000c700 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c700 0x100>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_I2C4>;
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clock-names = "div-clk";
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resets = <&tegra_car 103>;
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reset-names = "i2c";
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status = "disabled";
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};
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i2c@7000d000 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000d000 0x100>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_I2C5>;
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clock-names = "div-clk";
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resets = <&tegra_car 47>;
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reset-names = "i2c";
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status = "disabled";
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};
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spi@7000d400 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000d400 0x200>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 15>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_SBC1>;
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clock-names = "spi";
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resets = <&tegra_car 41>;
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reset-names = "spi";
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status = "disabled";
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};
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spi@7000d600 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000d600 0x200>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 16>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_SBC2>;
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clock-names = "spi";
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resets = <&tegra_car 44>;
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reset-names = "spi";
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status = "disabled";
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};
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spi@7000d800 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000d800 0x200>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 17>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_SBC3>;
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clock-names = "spi";
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resets = <&tegra_car 46>;
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reset-names = "spi";
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status = "disabled";
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};
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spi@7000da00 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000da00 0x200>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 18>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_SBC4>;
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clock-names = "spi";
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resets = <&tegra_car 68>;
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reset-names = "spi";
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status = "disabled";
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};
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spi@7000dc00 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000dc00 0x200>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 27>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_SBC5>;
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clock-names = "spi";
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resets = <&tegra_car 104>;
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reset-names = "spi";
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status = "disabled";
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};
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spi@7000de00 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000de00 0x200>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 28>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_SBC6>;
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clock-names = "spi";
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resets = <&tegra_car 105>;
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reset-names = "spi";
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status = "disabled";
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};
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rtc {
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compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_RTC>;
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};
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kbc {
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compatible = "nvidia,tegra114-kbc";
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reg = <0x7000e200 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_KBC>;
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resets = <&tegra_car 36>;
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reset-names = "kbc";
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status = "disabled";
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};
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pmc {
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compatible = "nvidia,tegra114-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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};
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iommu {
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compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
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reg = <0x70019010 0x02c
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0x700191f0 0x010
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0x70019228 0x074>;
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nvidia,#asids = <4>;
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dma-window = <0 0x40000000>;
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nvidia,swgroups = <0x18659fe>;
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nvidia,ahb = <&ahb>;
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};
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ahub {
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compatible = "nvidia,tegra114-ahub";
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reg = <0x70080000 0x200>,
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<0x70080200 0x100>,
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<0x70081000 0x200>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
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<&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
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<&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
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<&apbdma 29>;
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clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
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<&tegra_car TEGRA114_CLK_APBIF>,
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<&tegra_car TEGRA114_CLK_I2S0>,
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<&tegra_car TEGRA114_CLK_I2S1>,
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<&tegra_car TEGRA114_CLK_I2S2>,
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<&tegra_car TEGRA114_CLK_I2S3>,
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<&tegra_car TEGRA114_CLK_I2S4>,
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<&tegra_car TEGRA114_CLK_DAM0>,
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<&tegra_car TEGRA114_CLK_DAM1>,
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<&tegra_car TEGRA114_CLK_DAM2>,
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<&tegra_car TEGRA114_CLK_SPDIF_IN>,
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<&tegra_car TEGRA114_CLK_AMX>,
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<&tegra_car TEGRA114_CLK_ADX>;
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clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
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"i2s3", "i2s4", "dam0", "dam1", "dam2",
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"spdif_in", "amx", "adx";
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resets = <&tegra_car 106>, /* d_audio */
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<&tegra_car 107>, /* apbif */
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<&tegra_car 30>, /* i2s0 */
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<&tegra_car 11>, /* i2s1 */
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<&tegra_car 18>, /* i2s2 */
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<&tegra_car 101>, /* i2s3 */
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<&tegra_car 102>, /* i2s4 */
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<&tegra_car 108>, /* dam0 */
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<&tegra_car 109>, /* dam1 */
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<&tegra_car 110>, /* dam2 */
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<&tegra_car 10>, /* spdif */
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<&tegra_car 153>, /* amx */
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<&tegra_car 154>; /* adx */
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reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
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"i2s3", "i2s4", "dam0", "dam1", "dam2",
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"spdif", "amx", "adx";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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tegra_i2s0: i2s@70080300 {
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compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
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reg = <0x70080300 0x100>;
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nvidia,ahub-cif-ids = <4 4>;
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clocks = <&tegra_car TEGRA114_CLK_I2S0>;
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resets = <&tegra_car 30>;
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reset-names = "i2s";
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status = "disabled";
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};
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tegra_i2s1: i2s@70080400 {
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compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
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reg = <0x70080400 0x100>;
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nvidia,ahub-cif-ids = <5 5>;
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clocks = <&tegra_car TEGRA114_CLK_I2S1>;
|
|
resets = <&tegra_car 11>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s2: i2s@70080500 {
|
|
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
|
|
reg = <0x70080500 0x100>;
|
|
nvidia,ahub-cif-ids = <6 6>;
|
|
clocks = <&tegra_car TEGRA114_CLK_I2S2>;
|
|
resets = <&tegra_car 18>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s3: i2s@70080600 {
|
|
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
|
|
reg = <0x70080600 0x100>;
|
|
nvidia,ahub-cif-ids = <7 7>;
|
|
clocks = <&tegra_car TEGRA114_CLK_I2S3>;
|
|
resets = <&tegra_car 101>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s4: i2s@70080700 {
|
|
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
|
|
reg = <0x70080700 0x100>;
|
|
nvidia,ahub-cif-ids = <8 8>;
|
|
clocks = <&tegra_car TEGRA114_CLK_I2S4>;
|
|
resets = <&tegra_car 102>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
sdhci@78000000 {
|
|
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
|
|
reg = <0x78000000 0x200>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
|
|
resets = <&tegra_car 14>;
|
|
reset-names = "sdhci";
|
|
status = "disable";
|
|
};
|
|
|
|
sdhci@78000200 {
|
|
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
|
|
reg = <0x78000200 0x200>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
|
|
resets = <&tegra_car 9>;
|
|
reset-names = "sdhci";
|
|
status = "disable";
|
|
};
|
|
|
|
sdhci@78000400 {
|
|
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
|
|
reg = <0x78000400 0x200>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
|
|
resets = <&tegra_car 69>;
|
|
reset-names = "sdhci";
|
|
status = "disable";
|
|
};
|
|
|
|
sdhci@78000600 {
|
|
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
|
|
reg = <0x78000600 0x200>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
|
|
resets = <&tegra_car 15>;
|
|
reset-names = "sdhci";
|
|
status = "disable";
|
|
};
|
|
|
|
usb@7d000000 {
|
|
compatible = "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x7d000000 0x4000>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA114_CLK_USBD>;
|
|
resets = <&tegra_car 22>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy1: usb-phy@7d000000 {
|
|
compatible = "nvidia,tegra30-usb-phy";
|
|
reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA114_CLK_USBD>,
|
|
<&tegra_car TEGRA114_CLK_PLL_U>,
|
|
<&tegra_car TEGRA114_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
nvidia,hssync-start-delay = <0>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <0>;
|
|
nvidia,xcvr-lsrslew = <3>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
nvidia,xcvr-hsslew = <12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7d008000 {
|
|
compatible = "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x7d008000 0x4000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA114_CLK_USB3>;
|
|
resets = <&tegra_car 59>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy3: usb-phy@7d008000 {
|
|
compatible = "nvidia,tegra30-usb-phy";
|
|
reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA114_CLK_USB3>,
|
|
<&tegra_car TEGRA114_CLK_PLL_U>,
|
|
<&tegra_car TEGRA114_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
nvidia,hssync-start-delay = <0>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <0>;
|
|
nvidia,xcvr-lsrslew = <3>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
nvidia,xcvr-hsslew = <12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <1>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <2>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts =
|
|
<GIC_PPI 13
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|