forked from Minki/linux
3d5134ee83
This rewrites pretty much from scratch the handling of MMIO and PIO space allocations on powerpc64. The main goals are: - Get rid of imalloc and use more common code where possible - Simplify the current mess so that PIO space is allocated and mapped in a single place for PCI bridges - Handle allocation constraints of PIO for all bridges including hot plugged ones within the 2GB space reserved for IO ports, so that devices on hotplugged busses will now work with drivers that assume IO ports fit in an int. - Cleanup and separate tracking of the ISA space in the reserved low 64K of IO space. No ISA -> Nothing mapped there. I booted a cell blade with IDE on PIO and MMIO and a dual G5 so far, that's it :-) With this patch, all allocations are done using the code in mm/vmalloc.c, though we use the low level __get_vm_area with explicit start/stop constraints in order to manage separate areas for vmalloc/vmap, ioremap, and PCI IOs. This greatly simplifies a lot of things, as you can see in the diffstat of that patch :-) A new pair of functions pcibios_map/unmap_io_space() now replace all of the previous code that used to manipulate PCI IOs space. The allocation is done at mapping time, which is now called from scan_phb's, just before the devices are probed (instead of after, which is by itself a bug fix). The only other caller is the PCI hotplug code for hot adding PCI-PCI bridges (slots). imalloc is gone, as is the "sub-allocation" thing, but I do beleive that hotplug should still work in the sense that the space allocation is always done by the PHB, but if you unmap a child bus of this PHB (which seems to be possible), then the code should properly tear down all the HPTE mappings for that area of the PHB allocated IO space. I now always reserve the first 64K of IO space for the bridge with the ISA bus on it. I have moved the code for tracking ISA in a separate file which should also make it smarter if we ever are capable of hot unplugging or re-plugging an ISA bridge. This should have a side effect on platforms like powermac where VGA IOs will no longer work. This is done on purpose though as they would have worked semi-randomly before. The idea at this point is to isolate drivers that might need to access those and fix them by providing a proper function to obtain an offset to the legacy IOs of a given bus. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
218 lines
5.6 KiB
C
218 lines
5.6 KiB
C
/*
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* PCI Dynamic LPAR, PCI Hot Plug and PCI EEH recovery code
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* for RPA-compliant PPC64 platform.
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* Copyright (C) 2003 Linda Xie <lxie@us.ibm.com>
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* Copyright (C) 2005 International Business Machines
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*
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* Updates, 2005, John Rose <johnrose@austin.ibm.com>
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* Updates, 2005, Linas Vepstas <linas@austin.ibm.com>
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/pci.h>
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#include <asm/pci-bridge.h>
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#include <asm/ppc-pci.h>
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#include <asm/firmware.h>
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#include <asm/eeh.h>
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static struct pci_bus *
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find_bus_among_children(struct pci_bus *bus,
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struct device_node *dn)
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{
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struct pci_bus *child = NULL;
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struct list_head *tmp;
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struct device_node *busdn;
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busdn = pci_bus_to_OF_node(bus);
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if (busdn == dn)
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return bus;
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list_for_each(tmp, &bus->children) {
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child = find_bus_among_children(pci_bus_b(tmp), dn);
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if (child)
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break;
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};
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return child;
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}
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struct pci_bus *
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pcibios_find_pci_bus(struct device_node *dn)
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{
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struct pci_dn *pdn = dn->data;
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if (!pdn || !pdn->phb || !pdn->phb->bus)
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return NULL;
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return find_bus_among_children(pdn->phb->bus, dn);
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}
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EXPORT_SYMBOL_GPL(pcibios_find_pci_bus);
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/**
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* pcibios_remove_pci_devices - remove all devices under this bus
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*
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* Remove all of the PCI devices under this bus both from the
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* linux pci device tree, and from the powerpc EEH address cache.
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*/
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void
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pcibios_remove_pci_devices(struct pci_bus *bus)
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{
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struct pci_dev *dev, *tmp;
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list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
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eeh_remove_bus_device(dev);
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pci_remove_bus_device(dev);
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}
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}
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EXPORT_SYMBOL_GPL(pcibios_remove_pci_devices);
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/* Must be called before pci_bus_add_devices */
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void
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pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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/*
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* Skip already-present devices (which are on the
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* global device list.)
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*/
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if (list_empty(&dev->global_list)) {
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int i;
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/* Fill device archdata and setup iommu table */
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pcibios_setup_new_device(dev);
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if(fix_bus)
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pcibios_fixup_device_resources(dev, bus);
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pci_read_irq_line(dev);
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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struct resource *r = &dev->resource[i];
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if (r->parent || !r->start || !r->flags)
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continue;
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pci_claim_resource(dev, i);
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}
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}
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}
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}
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EXPORT_SYMBOL_GPL(pcibios_fixup_new_pci_devices);
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static int
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pcibios_pci_config_bridge(struct pci_dev *dev)
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{
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u8 sec_busno;
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struct pci_bus *child_bus;
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/* Get busno of downstream bus */
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pci_read_config_byte(dev, PCI_SECONDARY_BUS, &sec_busno);
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/* Add to children of PCI bridge dev->bus */
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child_bus = pci_add_new_bus(dev->bus, dev, sec_busno);
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if (!child_bus) {
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printk (KERN_ERR "%s: could not add second bus\n", __FUNCTION__);
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return -EIO;
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}
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sprintf(child_bus->name, "PCI Bus #%02x", child_bus->number);
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pci_scan_child_bus(child_bus);
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/* Fixup new pci devices without touching bus struct */
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pcibios_fixup_new_pci_devices(child_bus, 0);
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/* Make the discovered devices available */
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pci_bus_add_devices(child_bus);
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eeh_add_device_tree_late(child_bus);
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return 0;
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}
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/**
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* pcibios_add_pci_devices - adds new pci devices to bus
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*
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* This routine will find and fixup new pci devices under
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* the indicated bus. This routine presumes that there
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* might already be some devices under this bridge, so
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* it carefully tries to add only new devices. (And that
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* is how this routine differs from other, similar pcibios
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* routines.)
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*/
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void
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pcibios_add_pci_devices(struct pci_bus * bus)
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{
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int slotno, num, mode;
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struct pci_dev *dev;
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struct device_node *dn = pci_bus_to_OF_node(bus);
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eeh_add_device_tree_early(dn);
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mode = PCI_PROBE_NORMAL;
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if (ppc_md.pci_probe_mode)
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mode = ppc_md.pci_probe_mode(bus);
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if (mode == PCI_PROBE_DEVTREE) {
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/* use ofdt-based probe */
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of_scan_bus(dn, bus);
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if (!list_empty(&bus->devices)) {
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pcibios_fixup_new_pci_devices(bus, 0);
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pci_bus_add_devices(bus);
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eeh_add_device_tree_late(bus);
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}
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} else if (mode == PCI_PROBE_NORMAL) {
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/* use legacy probe */
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slotno = PCI_SLOT(PCI_DN(dn->child)->devfn);
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num = pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
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if (num) {
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pcibios_fixup_new_pci_devices(bus, 1);
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pci_bus_add_devices(bus);
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eeh_add_device_tree_late(bus);
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}
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list_for_each_entry(dev, &bus->devices, bus_list)
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if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
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pcibios_pci_config_bridge(dev);
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}
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}
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EXPORT_SYMBOL_GPL(pcibios_add_pci_devices);
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struct pci_controller * __devinit init_phb_dynamic(struct device_node *dn)
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{
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struct pci_controller *phb;
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int primary;
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primary = list_empty(&hose_list);
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phb = pcibios_alloc_controller(dn);
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if (!phb)
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return NULL;
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rtas_setup_phb(phb);
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pci_process_bridge_OF_ranges(phb, dn, 0);
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pci_devs_phb_init_dynamic(phb);
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if (dn->child)
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eeh_add_device_tree_early(dn);
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scan_phb(phb);
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pcibios_fixup_new_pci_devices(phb->bus, 0);
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pci_bus_add_devices(phb->bus);
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eeh_add_device_tree_late(phb->bus);
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return phb;
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}
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EXPORT_SYMBOL_GPL(init_phb_dynamic);
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