forked from Minki/linux
4732f2444a
The new module parameter to control PMU virtualization should apply
to Intel as well as AMD, for situations where userspace is not trusted.
If the module parameter allows PMU virtualization, there could be a
new KVM_CAP or guest CPUID bits whereby userspace can enable/disable
PMU virtualization on a per-VM basis.
If the module parameter does not allow PMU virtualization, there
should be no userspace override, since we have no precedent for
authorizing that kind of override. If it's false, other counter-based
profiling features (such as LBR including the associated CPUID bits
if any) will not be exposed.
Change its name from "pmu" to "enable_pmu" as we have temporary
variables with the same name in our code like "struct kvm_pmu *pmu".
Fixes: b1d66dad65 ("KVM: x86/svm: Add module param to control PMU virtualization")
Suggested-by : Jim Mattson <jmattson@google.com>
Signed-off-by: Like Xu <likexu@tencent.com>
Message-Id: <20220111073823.21885-1-likexu@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
497 lines
14 KiB
C
497 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ARCH_X86_KVM_X86_H
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#define ARCH_X86_KVM_X86_H
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#include <linux/kvm_host.h>
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#include <asm/mce.h>
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#include <asm/pvclock.h>
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#include "kvm_cache_regs.h"
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#include "kvm_emulate.h"
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void kvm_spurious_fault(void);
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static __always_inline void kvm_guest_enter_irqoff(void)
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{
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/*
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* VMENTER enables interrupts (host state), but the kernel state is
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* interrupts disabled when this is invoked. Also tell RCU about
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* it. This is the same logic as for exit_to_user_mode().
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*
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* This ensures that e.g. latency analysis on the host observes
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* guest mode as interrupt enabled.
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*
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* guest_enter_irqoff() informs context tracking about the
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* transition to guest mode and if enabled adjusts RCU state
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* accordingly.
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*/
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instrumentation_begin();
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trace_hardirqs_on_prepare();
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lockdep_hardirqs_on_prepare(CALLER_ADDR0);
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instrumentation_end();
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guest_enter_irqoff();
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lockdep_hardirqs_on(CALLER_ADDR0);
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}
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static __always_inline void kvm_guest_exit_irqoff(void)
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{
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/*
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* VMEXIT disables interrupts (host state), but tracing and lockdep
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* have them in state 'on' as recorded before entering guest mode.
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* Same as enter_from_user_mode().
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*
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* context_tracking_guest_exit() restores host context and reinstates
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* RCU if enabled and required.
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*
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* This needs to be done immediately after VM-Exit, before any code
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* that might contain tracepoints or call out to the greater world,
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* e.g. before x86_spec_ctrl_restore_host().
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*/
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lockdep_hardirqs_off(CALLER_ADDR0);
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context_tracking_guest_exit();
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instrumentation_begin();
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trace_hardirqs_off_finish();
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instrumentation_end();
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}
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#define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \
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({ \
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bool failed = (consistency_check); \
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if (failed) \
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trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
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failed; \
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})
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#define KVM_DEFAULT_PLE_GAP 128
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#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
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#define KVM_DEFAULT_PLE_WINDOW_GROW 2
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#define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
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#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
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#define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
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#define KVM_SVM_DEFAULT_PLE_WINDOW 3000
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static inline unsigned int __grow_ple_window(unsigned int val,
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unsigned int base, unsigned int modifier, unsigned int max)
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{
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u64 ret = val;
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if (modifier < 1)
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return base;
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if (modifier < base)
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ret *= modifier;
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else
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ret += modifier;
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return min(ret, (u64)max);
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}
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static inline unsigned int __shrink_ple_window(unsigned int val,
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unsigned int base, unsigned int modifier, unsigned int min)
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{
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if (modifier < 1)
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return base;
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if (modifier < base)
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val /= modifier;
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else
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val -= modifier;
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return max(val, min);
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}
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#define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
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void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu);
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int kvm_check_nested_events(struct kvm_vcpu *vcpu);
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static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.exception.pending = false;
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vcpu->arch.exception.injected = false;
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}
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static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
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bool soft)
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{
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vcpu->arch.interrupt.injected = true;
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vcpu->arch.interrupt.soft = soft;
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vcpu->arch.interrupt.nr = vector;
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}
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static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.interrupt.injected = false;
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}
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static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
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vcpu->arch.nmi_injected;
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}
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static inline bool kvm_exception_is_soft(unsigned int nr)
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{
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return (nr == BP_VECTOR) || (nr == OF_VECTOR);
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}
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static inline bool is_protmode(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
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}
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static inline int is_long_mode(struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_X86_64
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return vcpu->arch.efer & EFER_LMA;
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#else
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return 0;
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#endif
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}
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static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
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{
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int cs_db, cs_l;
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WARN_ON_ONCE(vcpu->arch.guest_state_protected);
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if (!is_long_mode(vcpu))
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return false;
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static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
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return cs_l;
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}
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static inline bool is_64_bit_hypercall(struct kvm_vcpu *vcpu)
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{
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/*
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* If running with protected guest state, the CS register is not
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* accessible. The hypercall register values will have had to been
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* provided in 64-bit mode, so assume the guest is in 64-bit.
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*/
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return vcpu->arch.guest_state_protected || is_64_bit_mode(vcpu);
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}
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static inline bool x86_exception_has_error_code(unsigned int vector)
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{
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static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
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BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
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BIT(PF_VECTOR) | BIT(AC_VECTOR);
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return (1U << vector) & exception_has_error_code;
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}
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static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
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}
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static inline int is_pae(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
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}
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static inline int is_pse(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
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}
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static inline int is_paging(struct kvm_vcpu *vcpu)
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{
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return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
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}
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static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
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{
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return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
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}
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static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
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}
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static inline u64 get_canonical(u64 la, u8 vaddr_bits)
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{
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return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
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}
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static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
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{
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return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
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}
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static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
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gva_t gva, gfn_t gfn, unsigned access)
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{
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u64 gen = kvm_memslots(vcpu->kvm)->generation;
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if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
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return;
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/*
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* If this is a shadow nested page table, the "GVA" is
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* actually a nGPA.
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*/
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vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
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vcpu->arch.mmio_access = access;
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vcpu->arch.mmio_gfn = gfn;
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vcpu->arch.mmio_gen = gen;
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}
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static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
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}
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/*
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* Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
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* clear all mmio cache info.
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*/
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#define MMIO_GVA_ANY (~(gva_t)0)
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static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
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{
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if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
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return;
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vcpu->arch.mmio_gva = 0;
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}
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static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
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{
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if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
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vcpu->arch.mmio_gva == (gva & PAGE_MASK))
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return true;
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return false;
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}
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static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
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{
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if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
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vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
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return true;
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return false;
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}
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static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg)
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{
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unsigned long val = kvm_register_read_raw(vcpu, reg);
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return is_64_bit_mode(vcpu) ? val : (u32)val;
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}
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static inline void kvm_register_write(struct kvm_vcpu *vcpu,
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int reg, unsigned long val)
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{
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if (!is_64_bit_mode(vcpu))
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val = (u32)val;
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return kvm_register_write_raw(vcpu, reg, val);
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}
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static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
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{
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return !(kvm->arch.disabled_quirks & quirk);
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}
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static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu)
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{
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return is_smm(vcpu) || static_call(kvm_x86_apic_init_signal_blocked)(vcpu);
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}
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void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
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u64 get_kvmclock_ns(struct kvm *kvm);
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int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
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gva_t addr, void *val, unsigned int bytes,
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struct x86_exception *exception);
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int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
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gva_t addr, void *val, unsigned int bytes,
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struct x86_exception *exception);
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int handle_ud(struct kvm_vcpu *vcpu);
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void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
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void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
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u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
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bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
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bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
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int page_num);
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bool kvm_vector_hashing_enabled(void);
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void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
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int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
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void *insn, int insn_len);
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int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
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int emulation_type, void *insn, int insn_len);
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fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
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extern u64 host_xcr0;
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extern u64 supported_xcr0;
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extern u64 host_xss;
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extern u64 supported_xss;
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extern bool enable_pmu;
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static inline bool kvm_mpx_supported(void)
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{
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return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
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== (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
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}
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extern unsigned int min_timer_period_us;
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extern bool enable_vmware_backdoor;
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extern int pi_inject_timer;
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extern bool report_ignored_msrs;
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static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
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{
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return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
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vcpu->arch.virtual_tsc_shift);
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}
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/* Same "calling convention" as do_div:
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* - divide (n << 32) by base
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* - put result in n
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* - return remainder
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*/
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#define do_shl32_div32(n, base) \
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({ \
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u32 __quot, __rem; \
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asm("divl %2" : "=a" (__quot), "=d" (__rem) \
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: "rm" (base), "0" (0), "1" ((u32) n)); \
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n = __quot; \
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__rem; \
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})
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static inline bool kvm_mwait_in_guest(struct kvm *kvm)
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{
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return kvm->arch.mwait_in_guest;
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}
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static inline bool kvm_hlt_in_guest(struct kvm *kvm)
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{
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return kvm->arch.hlt_in_guest;
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}
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static inline bool kvm_pause_in_guest(struct kvm *kvm)
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{
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return kvm->arch.pause_in_guest;
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}
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static inline bool kvm_cstate_in_guest(struct kvm *kvm)
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{
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return kvm->arch.cstate_in_guest;
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}
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DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu);
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static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu)
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{
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__this_cpu_write(current_vcpu, vcpu);
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}
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static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
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{
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__this_cpu_write(current_vcpu, NULL);
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}
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static inline bool kvm_pat_valid(u64 data)
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{
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if (data & 0xF8F8F8F8F8F8F8F8ull)
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return false;
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/* 0, 1, 4, 5, 6, 7 are valid values. */
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return (data | ((data & 0x0202020202020202ull) << 1)) == data;
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}
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static inline bool kvm_dr7_valid(u64 data)
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{
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/* Bits [63:32] are reserved */
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return !(data >> 32);
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}
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static inline bool kvm_dr6_valid(u64 data)
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{
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/* Bits [63:32] are reserved */
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return !(data >> 32);
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}
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/*
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* Trigger machine check on the host. We assume all the MSRs are already set up
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* by the CPU and that we still run on the same CPU as the MCE occurred on.
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* We pass a fake environment to the machine check handler because we want
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* the guest to be always treated like user space, no matter what context
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* it used internally.
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*/
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static inline void kvm_machine_check(void)
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{
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#if defined(CONFIG_X86_MCE)
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struct pt_regs regs = {
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.cs = 3, /* Fake ring 3 no matter what the guest ran on */
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.flags = X86_EFLAGS_IF,
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};
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do_machine_check(®s);
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#endif
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}
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void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
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void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
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int kvm_spec_ctrl_test_value(u64 value);
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bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
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int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
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struct x86_exception *e);
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int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
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bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
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/*
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* Internal error codes that are used to indicate that MSR emulation encountered
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* an error that should result in #GP in the guest, unless userspace
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* handles it.
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*/
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#define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */
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#define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */
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#define __cr4_reserved_bits(__cpu_has, __c) \
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({ \
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u64 __reserved_bits = CR4_RESERVED_BITS; \
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\
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if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
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__reserved_bits |= X86_CR4_OSXSAVE; \
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if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
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__reserved_bits |= X86_CR4_SMEP; \
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if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
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__reserved_bits |= X86_CR4_SMAP; \
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if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
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__reserved_bits |= X86_CR4_FSGSBASE; \
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if (!__cpu_has(__c, X86_FEATURE_PKU)) \
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__reserved_bits |= X86_CR4_PKE; \
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if (!__cpu_has(__c, X86_FEATURE_LA57)) \
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__reserved_bits |= X86_CR4_LA57; \
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if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
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__reserved_bits |= X86_CR4_UMIP; \
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if (!__cpu_has(__c, X86_FEATURE_VMX)) \
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__reserved_bits |= X86_CR4_VMXE; \
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if (!__cpu_has(__c, X86_FEATURE_PCID)) \
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__reserved_bits |= X86_CR4_PCIDE; \
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__reserved_bits; \
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})
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int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
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void *dst);
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int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
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void *dst);
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int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
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unsigned int port, void *data, unsigned int count,
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int in);
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#endif
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