forked from Minki/linux
e0b2f8cff1
Updated interface between the driver and the SMU controller. Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
482 lines
15 KiB
C
482 lines
15 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU9_DRIVER_IF_H
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#define SMU9_DRIVER_IF_H
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#include "smu9.h"
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/**** IMPORTANT ***
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* SMU TEAM: Always increment the interface version if
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* any structure is changed in this file
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*/
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#define SMU9_DRIVER_IF_VERSION 0xD
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#define PPTABLE_V10_SMU_VERSION 1
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#define NUM_GFXCLK_DPM_LEVELS 8
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#define NUM_UVD_DPM_LEVELS 8
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#define NUM_VCE_DPM_LEVELS 8
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#define NUM_MP0CLK_DPM_LEVELS 8
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#define NUM_UCLK_DPM_LEVELS 4
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#define NUM_SOCCLK_DPM_LEVELS 8
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#define NUM_DCEFCLK_DPM_LEVELS 8
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#define NUM_LINK_LEVELS 2
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#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
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#define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
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#define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
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#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
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#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
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#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
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#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
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#define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
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#define MIN_GFXCLK_DPM_LEVEL 0
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#define MIN_UVD_DPM_LEVEL 0
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#define MIN_VCE_DPM_LEVEL 0
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#define MIN_MP0CLK_DPM_LEVEL 0
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#define MIN_UCLK_DPM_LEVEL 0
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#define MIN_SOCCLK_DPM_LEVEL 0
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#define MIN_DCEFCLK_DPM_LEVEL 0
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#define MIN_LINK_DPM_LEVEL 0
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#define NUM_EVV_VOLTAGE_LEVELS 8
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#define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
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#define MIN_EVV_VOLTAGE_LEVEL 0
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#define NUM_PSP_LEVEL_MAP 4
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/* Gemini Modes */
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#define PPSMC_GeminiModeNone 0 /* Single GPU board */
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#define PPSMC_GeminiModeMaster 1 /* Master GPU on a Gemini board */
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#define PPSMC_GeminiModeSlave 2 /* Slave GPU on a Gemini board */
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/* Voltage Modes for DPMs */
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#define VOLTAGE_MODE_AVFS_INTERPOLATE 0
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#define VOLTAGE_MODE_AVFS_WORST_CASE 1
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#define VOLTAGE_MODE_STATIC 2
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typedef struct {
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uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
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uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */
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uint16_t SsSlewFrac;
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uint8_t SsOn;
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uint8_t Did; /* DID */
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} PllSetting_t;
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typedef struct {
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int32_t a0;
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int32_t a1;
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int32_t a2;
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uint8_t a0_shift;
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uint8_t a1_shift;
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uint8_t a2_shift;
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uint8_t padding;
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} GbVdroopTable_t;
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typedef struct {
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int32_t m1;
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int32_t m2;
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int32_t b;
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uint8_t m1_shift;
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uint8_t m2_shift;
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uint8_t b_shift;
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uint8_t padding;
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} QuadraticInt_t;
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#define NUM_DSPCLK_LEVELS 8
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typedef enum {
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DSPCLK_DCEFCLK = 0,
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DSPCLK_DISPCLK,
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DSPCLK_PIXCLK,
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DSPCLK_PHYCLK,
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DSPCLK_COUNT,
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} DSPCLK_e;
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typedef struct {
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uint16_t Freq; /* in MHz */
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uint16_t Vid; /* min voltage in SVI2 VID */
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} DisplayClockTable_t;
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typedef struct {
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/* PowerTune */
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uint16_t SocketPowerLimit; /* Watts */
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uint16_t TdcLimit; /* Amps */
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uint16_t EdcLimit; /* Amps */
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uint16_t TedgeLimit; /* Celcius */
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uint16_t ThotspotLimit; /* Celcius */
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uint16_t ThbmLimit; /* Celcius */
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uint16_t Tvr_socLimit; /* Celcius */
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uint16_t Tvr_memLimit; /* Celcius */
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uint16_t Tliquid1Limit; /* Celcius */
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uint16_t Tliquid2Limit; /* Celcius */
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uint16_t TplxLimit; /* Celcius */
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uint16_t LoadLineResistance; /* in mOhms */
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uint32_t FitLimit; /* Failures in time (failures per million parts over the defined lifetime) */
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/* External Component Communication Settings */
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uint8_t Liquid1_I2C_address;
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uint8_t Liquid2_I2C_address;
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uint8_t Vr_I2C_address;
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uint8_t Plx_I2C_address;
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uint8_t GeminiMode;
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uint8_t spare17[3];
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uint32_t GeminiApertureHigh;
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uint32_t GeminiApertureLow;
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uint8_t Liquid_I2C_LineSCL;
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uint8_t Liquid_I2C_LineSDA;
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uint8_t Vr_I2C_LineSCL;
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uint8_t Vr_I2C_LineSDA;
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uint8_t Plx_I2C_LineSCL;
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uint8_t Plx_I2C_LineSDA;
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uint8_t paddingx[2];
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/* ULV Settings */
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uint8_t UlvOffsetVid; /* SVI2 VID */
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uint8_t UlvSmnclkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
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uint8_t UlvMp1clkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
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uint8_t UlvGfxclkBypass; /* 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV */
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/* VDDCR_SOC Voltages */
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uint8_t SocVid[NUM_EVV_VOLTAGE_LEVELS];
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/* This is the minimum voltage needed to run the SOC. */
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uint8_t MinVoltageVid; /* Minimum Voltage ("Vmin") of ASIC */
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uint8_t MaxVoltageVid; /* Maximum Voltage allowable */
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uint8_t MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltage change exceeds this value. */
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uint8_t padding8;
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uint8_t UlvPhaseSheddingPsi0; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
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uint8_t UlvPhaseSheddingPsi1; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
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uint8_t padding8_2[2];
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/* SOC Frequencies */
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PllSetting_t GfxclkLevel [NUM_GFXCLK_DPM_LEVELS];
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uint8_t SocclkDid [NUM_SOCCLK_DPM_LEVELS]; /* DID */
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uint8_t SocDpmVoltageIndex [NUM_SOCCLK_DPM_LEVELS];
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uint8_t VclkDid [NUM_UVD_DPM_LEVELS]; /* DID */
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uint8_t DclkDid [NUM_UVD_DPM_LEVELS]; /* DID */
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uint8_t UvdDpmVoltageIndex [NUM_UVD_DPM_LEVELS];
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uint8_t EclkDid [NUM_VCE_DPM_LEVELS]; /* DID */
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uint8_t VceDpmVoltageIndex [NUM_VCE_DPM_LEVELS];
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uint8_t Mp0clkDid [NUM_MP0CLK_DPM_LEVELS]; /* DID */
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uint8_t Mp0DpmVoltageIndex [NUM_MP0CLK_DPM_LEVELS];
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DisplayClockTable_t DisplayClockTable[DSPCLK_COUNT][NUM_DSPCLK_LEVELS];
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QuadraticInt_t DisplayClock2Gfxclk[DSPCLK_COUNT];
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uint8_t GfxDpmVoltageMode;
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uint8_t SocDpmVoltageMode;
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uint8_t UclkDpmVoltageMode;
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uint8_t UvdDpmVoltageMode;
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uint8_t VceDpmVoltageMode;
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uint8_t Mp0DpmVoltageMode;
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uint8_t DisplayDpmVoltageMode;
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uint8_t padding8_3;
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uint16_t GfxclkSlewRate;
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uint16_t padding;
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uint32_t LowGfxclkInterruptThreshold; /* in units of 10KHz */
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/* Alpha parameters for clock averages. ("255"=1) */
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uint8_t GfxclkAverageAlpha;
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uint8_t SocclkAverageAlpha;
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uint8_t UclkAverageAlpha;
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uint8_t GfxActivityAverageAlpha;
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/* UCLK States */
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uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */
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PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */
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uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
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uint8_t LowestUclkReservedForUlv; /* Set this to 1 if UCLK DPM0 is reserved for ULV-mode only */
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uint8_t paddingUclk[3];
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uint16_t NumMemoryChannels; /* Used for memory bandwidth calculations */
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uint16_t MemoryChannelWidth; /* Used for memory bandwidth calculations */
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/* CKS Settings */
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uint8_t CksEnable[NUM_GFXCLK_DPM_LEVELS];
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uint8_t CksVidOffset[NUM_GFXCLK_DPM_LEVELS];
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/* MP0 Mapping Table */
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uint8_t PspLevelMap[NUM_PSP_LEVEL_MAP];
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/* Link DPM Settings */
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uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
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uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
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uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */
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uint8_t paddingLinkDpm[2];
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/* Fan Control */
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uint16_t FanStopTemp; /* Celcius */
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uint16_t FanStartTemp; /* Celcius */
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uint16_t FanGainEdge;
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uint16_t FanGainHotspot;
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uint16_t FanGainLiquid;
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uint16_t FanGainVrVddc;
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uint16_t FanGainVrMvdd;
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uint16_t FanGainPlx;
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uint16_t FanGainHbm;
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uint16_t FanPwmMin;
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uint16_t FanAcousticLimitRpm;
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uint16_t FanThrottlingRpm;
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uint16_t FanMaximumRpm;
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uint16_t FanTargetTemperature;
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uint16_t FanTargetGfxclk;
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uint8_t FanZeroRpmEnable;
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uint8_t FanSpare;
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/* The following are AFC override parameters. Leave at 0 to use FW defaults. */
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int16_t FuzzyFan_ErrorSetDelta;
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int16_t FuzzyFan_ErrorRateSetDelta;
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int16_t FuzzyFan_PwmSetDelta;
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uint16_t FuzzyFan_Reserved;
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/* GPIO Settings */
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uint8_t AcDcGpio; /* GPIO pin configured for AC/DC switching */
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uint8_t AcDcPolarity; /* GPIO polarity for AC/DC switching */
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uint8_t VR0HotGpio; /* GPIO pin configured for VR0 HOT event */
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uint8_t VR0HotPolarity; /* GPIO polarity for VR0 HOT event */
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uint8_t VR1HotGpio; /* GPIO pin configured for VR1 HOT event */
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uint8_t VR1HotPolarity; /* GPIO polarity for VR1 HOT event */
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uint8_t Padding1; /* replace GPIO pin configured for CTF */
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uint8_t Padding2; /* replace GPIO polarity for CTF */
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/* LED Display Settings */
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uint8_t LedPin0; /* GPIO number for LedPin[0] */
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uint8_t LedPin1; /* GPIO number for LedPin[1] */
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uint8_t LedPin2; /* GPIO number for LedPin[2] */
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uint8_t padding8_4;
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/* AVFS */
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uint8_t OverrideBtcGbCksOn;
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uint8_t OverrideAvfsGbCksOn;
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uint8_t PaddingAvfs8[2];
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GbVdroopTable_t BtcGbVdroopTableCksOn;
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GbVdroopTable_t BtcGbVdroopTableCksOff;
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QuadraticInt_t AvfsGbCksOn; /* Replacement equation */
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QuadraticInt_t AvfsGbCksOff; /* Replacement equation */
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uint8_t StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the final voltage calculation */
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/* Ageing Guardband Parameters */
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uint32_t AConstant[3];
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uint16_t DC_tol_sigma;
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uint16_t Platform_mean;
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uint16_t Platform_sigma;
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uint16_t PSM_Age_CompFactor;
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uint32_t DpmLevelPowerDelta;
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uint8_t EnableBoostState;
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uint8_t AConstant_Shift;
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uint8_t DC_tol_sigma_Shift;
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uint8_t PSM_Age_CompFactor_Shift;
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uint16_t BoostStartTemperature;
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uint16_t BoostStopTemperature;
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PllSetting_t GfxBoostState;
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uint32_t Reserved[14];
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/* Padding - ignore */
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uint32_t MmHubPadding[7]; /* SMU internal use */
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} PPTable_t;
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typedef struct {
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uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
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uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
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uint16_t MinUclk;
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uint16_t MaxUclk;
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uint8_t WmSetting;
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uint8_t Padding[3];
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} WatermarkRowGeneric_t;
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#define NUM_WM_RANGES 4
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typedef enum {
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WM_SOCCLK = 0,
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WM_DCEFCLK,
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WM_COUNT,
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} WM_CLOCK_e;
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typedef struct {
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/* Watermarks */
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WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
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uint32_t MmHubPadding[7]; /* SMU internal use */
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} Watermarks_t;
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#ifdef PPTABLE_V10_SMU_VERSION
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typedef struct {
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float AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
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float AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
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float AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
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float AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
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float DcBtcGb;
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uint32_t MmHubPadding[7]; /* SMU internal use */
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} AvfsTable_t;
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#else
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typedef struct {
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uint32_t AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
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uint32_t AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
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uint32_t AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
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uint32_t AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
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uint32_t DcBtcGb;
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uint32_t MmHubPadding[7]; /* SMU internal use */
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} AvfsTable_t;
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#endif
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typedef struct {
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uint16_t avgPsmCount[30];
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uint16_t minPsmCount[30];
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float avgPsmVoltage[30];
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float minPsmVoltage[30];
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uint32_t MmHubPadding[7]; /* SMU internal use */
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} AvfsDebugTable_t;
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typedef struct {
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uint8_t AvfsEn;
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uint8_t AvfsVersion;
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uint8_t Padding[2];
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uint32_t VFT0_m1; /* Q16.16 */
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uint32_t VFT0_m2; /* Q16.16 */
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uint32_t VFT0_b; /* Q16.16 */
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uint32_t VFT1_m1; /* Q16.16 */
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uint32_t VFT1_m2; /* Q16.16 */
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uint32_t VFT1_b; /* Q16.16 */
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uint32_t VFT2_m1; /* Q16.16 */
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uint32_t VFT2_m2; /* Q16.16 */
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uint32_t VFT2_b; /* Q16.16 */
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uint32_t AvfsGb0_m1; /* Q16.16 */
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uint32_t AvfsGb0_m2; /* Q16.16 */
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uint32_t AvfsGb0_b; /* Q16.16 */
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uint32_t AcBtcGb_m1; /* Q16.16 */
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uint32_t AcBtcGb_m2; /* Q16.16 */
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uint32_t AcBtcGb_b; /* Q16.16 */
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uint32_t AvfsTempCold;
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uint32_t AvfsTempMid;
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uint32_t AvfsTempHot;
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uint32_t InversionVoltage; /* in mV with 2 fractional bits */
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uint32_t P2V_m1; /* Q16.16 */
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uint32_t P2V_m2; /* Q16.16 */
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uint32_t P2V_b; /* Q16.16 */
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uint32_t P2VCharzFreq; /* in 10KHz units */
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uint32_t EnabledAvfsModules;
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uint32_t MmHubPadding[7]; /* SMU internal use */
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} AvfsFuseOverride_t;
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/* These defines are used with the following messages:
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* SMC_MSG_TransferTableDram2Smu
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* SMC_MSG_TransferTableSmu2Dram
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*/
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#define TABLE_PPTABLE 0
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#define TABLE_WATERMARKS 1
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#define TABLE_AVFS 2
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#define TABLE_AVFS_PSM_DEBUG 3
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#define TABLE_AVFS_FUSE_OVERRIDE 4
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#define TABLE_PMSTATUSLOG 5
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#define TABLE_COUNT 6
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/* These defines are used with the SMC_MSG_SetUclkFastSwitch message. */
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#define UCLK_SWITCH_SLOW 0
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#define UCLK_SWITCH_FAST 1
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/* GFX DIDT Configuration */
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#define SQ_Enable_MASK 0x1
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#define SQ_IR_MASK 0x2
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#define SQ_PCC_MASK 0x4
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#define SQ_EDC_MASK 0x8
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#define TCP_Enable_MASK 0x100
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#define TCP_IR_MASK 0x200
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#define TCP_PCC_MASK 0x400
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#define TCP_EDC_MASK 0x800
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#define TD_Enable_MASK 0x10000
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#define TD_IR_MASK 0x20000
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#define TD_PCC_MASK 0x40000
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#define TD_EDC_MASK 0x80000
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#define DB_Enable_MASK 0x1000000
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#define DB_IR_MASK 0x2000000
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#define DB_PCC_MASK 0x4000000
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#define DB_EDC_MASK 0x8000000
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#define SQ_Enable_SHIFT 0
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#define SQ_IR_SHIFT 1
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#define SQ_PCC_SHIFT 2
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#define SQ_EDC_SHIFT 3
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#define TCP_Enable_SHIFT 8
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#define TCP_IR_SHIFT 9
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#define TCP_PCC_SHIFT 10
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#define TCP_EDC_SHIFT 11
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#define TD_Enable_SHIFT 16
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#define TD_IR_SHIFT 17
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#define TD_PCC_SHIFT 18
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#define TD_EDC_SHIFT 19
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#define DB_Enable_SHIFT 24
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#define DB_IR_SHIFT 25
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#define DB_PCC_SHIFT 26
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#define DB_EDC_SHIFT 27
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#define REMOVE_FMAX_MARGIN_BIT 0x0
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#define REMOVE_DCTOL_MARGIN_BIT 0x1
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#define REMOVE_PLATFORM_MARGIN_BIT 0x2
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#endif
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