forked from Minki/linux
325089ab58
* Now that we properly set rx/tx latencies for AR5311 remove that old buggy part of code left inside ath5k_hw_tweak_initval_settings that was never executed (you can't have an RF5112 radio on a mac older than AR5212). Also use a magic value for 5311 PHY_SCAL value. Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
1160 lines
30 KiB
C
1160 lines
30 KiB
C
/*
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* Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
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* Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
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* Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
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* Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
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* Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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/*****************************\
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Reset functions and helpers
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\*****************************/
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#include <asm/unaligned.h>
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#include <linux/pci.h> /* To determine if a card is pci-e */
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#include <linux/log2.h>
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#include "ath5k.h"
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#include "reg.h"
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#include "base.h"
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#include "debug.h"
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/******************\
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* Helper functions *
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\******************/
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/*
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* Check if a register write has been completed
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*/
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int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
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bool is_set)
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{
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int i;
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u32 data;
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for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
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data = ath5k_hw_reg_read(ah, reg);
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if (is_set && (data & flag))
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break;
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else if ((data & flag) == val)
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break;
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udelay(15);
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}
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return (i <= 0) ? -EAGAIN : 0;
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}
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|
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/*************************\
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* Clock related functions *
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\*************************/
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/**
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* ath5k_hw_htoclock - Translate usec to hw clock units
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*
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* @ah: The &struct ath5k_hw
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* @usec: value in microseconds
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*/
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unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
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{
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struct ath_common *common = ath5k_hw_common(ah);
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return usec * common->clockrate;
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}
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/**
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* ath5k_hw_clocktoh - Translate hw clock units to usec
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* @clock: value in hw clock units
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*/
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unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
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{
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struct ath_common *common = ath5k_hw_common(ah);
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return clock / common->clockrate;
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}
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/**
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* ath5k_hw_init_core_clock - Initialize core clock
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*
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* @ah The &struct ath5k_hw
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*
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* Initialize core clock parameters (usec, usec32, latencies etc).
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*/
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static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
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{
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struct ieee80211_channel *channel = ah->ah_current_channel;
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struct ath_common *common = ath5k_hw_common(ah);
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u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
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/*
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* Set core clock frequency
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*/
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if (channel->hw_value & CHANNEL_5GHZ)
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clock = 40; /* 802.11a */
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else if (channel->hw_value & CHANNEL_CCK)
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clock = 22; /* 802.11b */
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else
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clock = 44; /* 802.11g */
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/* Use clock multiplier for non-default
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* bwmode */
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switch (ah->ah_bwmode) {
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case AR5K_BWMODE_40MHZ:
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clock *= 2;
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break;
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case AR5K_BWMODE_10MHZ:
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clock /= 2;
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break;
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case AR5K_BWMODE_5MHZ:
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clock /= 4;
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break;
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default:
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break;
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}
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common->clockrate = clock;
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/*
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* Set USEC parameters
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*/
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/* Set USEC counter on PCU*/
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usec = clock - 1;
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usec = AR5K_REG_SM(usec, AR5K_USEC_1);
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/* Set usec duration on DCU */
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if (ah->ah_version != AR5K_AR5210)
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AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
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AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
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clock);
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/* Set 32MHz USEC counter */
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if ((ah->ah_radio == AR5K_RF5112) ||
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(ah->ah_radio == AR5K_RF5413))
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/* Remain on 40MHz clock ? */
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sclock = 40 - 1;
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else
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sclock = 32 - 1;
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sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
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/*
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* Set tx/rx latencies
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*/
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usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
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txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
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rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
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/*
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* 5210 initvals don't include usec settings
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* so we need to use magic values here for
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* tx/rx latencies
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*/
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if (ah->ah_version == AR5K_AR5210) {
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/* same for turbo */
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txlat = AR5K_INIT_TX_LATENCY_5210;
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rxlat = AR5K_INIT_RX_LATENCY_5210;
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}
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if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
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/* 5311 has different tx/rx latency masks
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* from 5211, since we deal 5311 the same
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* as 5211 when setting initvals, shift
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* values here to their proper locations
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*
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* Note: Initvals indicate tx/rx/ latencies
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* are the same for turbo mode */
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txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
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rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
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} else
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switch (ah->ah_bwmode) {
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case AR5K_BWMODE_10MHZ:
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txlat = AR5K_REG_SM(txlat * 2,
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AR5K_USEC_TX_LATENCY_5211);
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rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
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AR5K_USEC_RX_LATENCY_5211);
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txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
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break;
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case AR5K_BWMODE_5MHZ:
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txlat = AR5K_REG_SM(txlat * 4,
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AR5K_USEC_TX_LATENCY_5211);
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rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
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AR5K_USEC_RX_LATENCY_5211);
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txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
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break;
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case AR5K_BWMODE_40MHZ:
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txlat = AR5K_INIT_TX_LAT_MIN;
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rxlat = AR5K_REG_SM(rxlat / 2,
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AR5K_USEC_RX_LATENCY_5211);
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txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
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break;
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default:
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break;
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}
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usec_reg = (usec | sclock | txlat | rxlat);
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ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
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/* On 5112 set tx frane to tx data start delay */
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if (ah->ah_radio == AR5K_RF5112) {
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AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
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AR5K_PHY_RF_CTL2_TXF2TXD_START,
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txf2txs);
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}
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}
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/*
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* If there is an external 32KHz crystal available, use it
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* as ref. clock instead of 32/40MHz clock and baseband clocks
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* to save power during sleep or restore normal 32/40MHz
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* operation.
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*
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* XXX: When operating on 32KHz certain PHY registers (27 - 31,
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* 123 - 127) require delay on access.
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*/
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static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
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{
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struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
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u32 scal, spending;
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/* Only set 32KHz settings if we have an external
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* 32KHz crystal present */
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if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
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AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
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enable) {
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/* 1 usec/cycle */
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AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
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/* Set up tsf increment on each cycle */
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AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
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/* Set baseband sleep control registers
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* and sleep control rate */
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ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
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if ((ah->ah_radio == AR5K_RF5112) ||
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(ah->ah_radio == AR5K_RF5413) ||
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(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
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spending = 0x14;
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else
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spending = 0x18;
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ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
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if ((ah->ah_radio == AR5K_RF5112) ||
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(ah->ah_radio == AR5K_RF5413) ||
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(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
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ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
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ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
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ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
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ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
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AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
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AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
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} else {
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ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
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ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
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ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
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ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
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AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
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AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
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}
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/* Enable sleep clock operation */
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AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
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AR5K_PCICFG_SLEEP_CLOCK_EN);
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} else {
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/* Disable sleep clock operation and
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* restore default parameters */
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AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
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AR5K_PCICFG_SLEEP_CLOCK_EN);
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AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
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AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
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|
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/* Set DAC/ADC delays */
|
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ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
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ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
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|
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if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
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scal = AR5K_PHY_SCAL_32MHZ_2417;
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else if (ee->ee_is_hb63)
|
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scal = AR5K_PHY_SCAL_32MHZ_HB63;
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else
|
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scal = AR5K_PHY_SCAL_32MHZ;
|
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ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
|
|
|
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ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
|
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ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
|
|
|
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if ((ah->ah_radio == AR5K_RF5112) ||
|
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(ah->ah_radio == AR5K_RF5413) ||
|
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(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
|
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spending = 0x14;
|
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else
|
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spending = 0x18;
|
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ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
|
|
|
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/* Set up tsf increment on each cycle */
|
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AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
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}
|
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}
|
|
|
|
|
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/*********************\
|
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* Reset/Sleep control *
|
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\*********************/
|
|
|
|
/*
|
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* Reset chipset
|
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*/
|
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static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
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{
|
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int ret;
|
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u32 mask = val ? val : ~0U;
|
|
|
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/* Read-and-clear RX Descriptor Pointer*/
|
|
ath5k_hw_reg_read(ah, AR5K_RXDP);
|
|
|
|
/*
|
|
* Reset the device and wait until success
|
|
*/
|
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ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
|
|
|
|
/* Wait at least 128 PCI clocks */
|
|
udelay(15);
|
|
|
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if (ah->ah_version == AR5K_AR5210) {
|
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val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
|
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| AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
|
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mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
|
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| AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
|
|
} else {
|
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val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
|
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mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
|
|
}
|
|
|
|
ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
|
|
|
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/*
|
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* Reset configuration register (for hw byte-swap). Note that this
|
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* is only set for big endian. We do the necessary magic in
|
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* AR5K_INIT_CFG.
|
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*/
|
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if ((val & AR5K_RESET_CTL_PCU) == 0)
|
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ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
|
|
|
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return ret;
|
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}
|
|
|
|
/*
|
|
* Sleep control
|
|
*/
|
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static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
|
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bool set_chip, u16 sleep_duration)
|
|
{
|
|
unsigned int i;
|
|
u32 staid, data;
|
|
|
|
staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
|
|
|
|
switch (mode) {
|
|
case AR5K_PM_AUTO:
|
|
staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
|
|
/* fallthrough */
|
|
case AR5K_PM_NETWORK_SLEEP:
|
|
if (set_chip)
|
|
ath5k_hw_reg_write(ah,
|
|
AR5K_SLEEP_CTL_SLE_ALLOW |
|
|
sleep_duration,
|
|
AR5K_SLEEP_CTL);
|
|
|
|
staid |= AR5K_STA_ID1_PWR_SV;
|
|
break;
|
|
|
|
case AR5K_PM_FULL_SLEEP:
|
|
if (set_chip)
|
|
ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
|
|
AR5K_SLEEP_CTL);
|
|
|
|
staid |= AR5K_STA_ID1_PWR_SV;
|
|
break;
|
|
|
|
case AR5K_PM_AWAKE:
|
|
|
|
staid &= ~AR5K_STA_ID1_PWR_SV;
|
|
|
|
if (!set_chip)
|
|
goto commit;
|
|
|
|
data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
|
|
|
|
/* If card is down we 'll get 0xffff... so we
|
|
* need to clean this up before we write the register
|
|
*/
|
|
if (data & 0xffc00000)
|
|
data = 0;
|
|
else
|
|
/* Preserve sleep duration etc */
|
|
data = data & ~AR5K_SLEEP_CTL_SLE;
|
|
|
|
ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
|
|
AR5K_SLEEP_CTL);
|
|
udelay(15);
|
|
|
|
for (i = 200; i > 0; i--) {
|
|
/* Check if the chip did wake up */
|
|
if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
|
|
AR5K_PCICFG_SPWR_DN) == 0)
|
|
break;
|
|
|
|
/* Wait a bit and retry */
|
|
udelay(50);
|
|
ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
|
|
AR5K_SLEEP_CTL);
|
|
}
|
|
|
|
/* Fail if the chip didn't wake up */
|
|
if (i == 0)
|
|
return -EIO;
|
|
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
commit:
|
|
ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Put device on hold
|
|
*
|
|
* Put MAC and Baseband on warm reset and
|
|
* keep that state (don't clean sleep control
|
|
* register). After this MAC and Baseband are
|
|
* disabled and a full reset is needed to come
|
|
* back. This way we save as much power as possible
|
|
* without putting the card on full sleep.
|
|
*/
|
|
int ath5k_hw_on_hold(struct ath5k_hw *ah)
|
|
{
|
|
struct pci_dev *pdev = ah->ah_sc->pdev;
|
|
u32 bus_flags;
|
|
int ret;
|
|
|
|
/* Make sure device is awake */
|
|
ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
|
|
if (ret) {
|
|
ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Put chipset on warm reset...
|
|
*
|
|
* Note: putting PCI core on warm reset on PCI-E cards
|
|
* results card to hang and always return 0xffff... so
|
|
* we ingore that flag for PCI-E cards. On PCI cards
|
|
* this flag gets cleared after 64 PCI clocks.
|
|
*/
|
|
bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
|
|
|
|
if (ah->ah_version == AR5K_AR5210) {
|
|
ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
|
|
AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
|
|
AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
|
|
mdelay(2);
|
|
} else {
|
|
ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
|
|
AR5K_RESET_CTL_BASEBAND | bus_flags);
|
|
}
|
|
|
|
if (ret) {
|
|
ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/* ...wakeup again!*/
|
|
ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
|
|
if (ret) {
|
|
ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
|
|
return ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Bring up MAC + PHY Chips and program PLL
|
|
* TODO: Half/Quarter rate support
|
|
*/
|
|
int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
|
|
{
|
|
struct pci_dev *pdev = ah->ah_sc->pdev;
|
|
u32 turbo, mode, clock, bus_flags;
|
|
int ret;
|
|
|
|
turbo = 0;
|
|
mode = 0;
|
|
clock = 0;
|
|
|
|
/* Wakeup the device */
|
|
ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
|
|
if (ret) {
|
|
ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Put chipset on warm reset...
|
|
*
|
|
* Note: putting PCI core on warm reset on PCI-E cards
|
|
* results card to hang and always return 0xffff... so
|
|
* we ingore that flag for PCI-E cards. On PCI cards
|
|
* this flag gets cleared after 64 PCI clocks.
|
|
*/
|
|
bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
|
|
|
|
if (ah->ah_version == AR5K_AR5210) {
|
|
ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
|
|
AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
|
|
AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
|
|
mdelay(2);
|
|
} else {
|
|
ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
|
|
AR5K_RESET_CTL_BASEBAND | bus_flags);
|
|
}
|
|
|
|
if (ret) {
|
|
ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/* ...wakeup again!...*/
|
|
ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
|
|
if (ret) {
|
|
ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
|
|
return ret;
|
|
}
|
|
|
|
/* ...clear reset control register and pull device out of
|
|
* warm reset */
|
|
if (ath5k_hw_nic_reset(ah, 0)) {
|
|
ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/* On initialization skip PLL programming since we don't have
|
|
* a channel / mode set yet */
|
|
if (initial)
|
|
return 0;
|
|
|
|
if (ah->ah_version != AR5K_AR5210) {
|
|
/*
|
|
* Get channel mode flags
|
|
*/
|
|
|
|
if (ah->ah_radio >= AR5K_RF5112) {
|
|
mode = AR5K_PHY_MODE_RAD_RF5112;
|
|
clock = AR5K_PHY_PLL_RF5112;
|
|
} else {
|
|
mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
|
|
clock = AR5K_PHY_PLL_RF5111; /*Zero*/
|
|
}
|
|
|
|
if (flags & CHANNEL_2GHZ) {
|
|
mode |= AR5K_PHY_MODE_FREQ_2GHZ;
|
|
clock |= AR5K_PHY_PLL_44MHZ;
|
|
|
|
if (flags & CHANNEL_CCK) {
|
|
mode |= AR5K_PHY_MODE_MOD_CCK;
|
|
} else if (flags & CHANNEL_OFDM) {
|
|
/* XXX Dynamic OFDM/CCK is not supported by the
|
|
* AR5211 so we set MOD_OFDM for plain g (no
|
|
* CCK headers) operation. We need to test
|
|
* this, 5211 might support ofdm-only g after
|
|
* all, there are also initial register values
|
|
* in the code for g mode (see initvals.c). */
|
|
if (ah->ah_version == AR5K_AR5211)
|
|
mode |= AR5K_PHY_MODE_MOD_OFDM;
|
|
else
|
|
mode |= AR5K_PHY_MODE_MOD_DYN;
|
|
} else {
|
|
ATH5K_ERR(ah->ah_sc,
|
|
"invalid radio modulation mode\n");
|
|
return -EINVAL;
|
|
}
|
|
} else if (flags & CHANNEL_5GHZ) {
|
|
mode |= AR5K_PHY_MODE_FREQ_5GHZ;
|
|
|
|
if (ah->ah_radio == AR5K_RF5413)
|
|
clock = AR5K_PHY_PLL_40MHZ_5413;
|
|
else
|
|
clock |= AR5K_PHY_PLL_40MHZ;
|
|
|
|
if (flags & CHANNEL_OFDM)
|
|
mode |= AR5K_PHY_MODE_MOD_OFDM;
|
|
else {
|
|
ATH5K_ERR(ah->ah_sc,
|
|
"invalid radio modulation mode\n");
|
|
return -EINVAL;
|
|
}
|
|
} else {
|
|
ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (flags & CHANNEL_TURBO)
|
|
turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
|
|
} else { /* Reset the device */
|
|
|
|
/* ...enable Atheros turbo mode if requested */
|
|
if (flags & CHANNEL_TURBO)
|
|
ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
|
|
AR5K_PHY_TURBO);
|
|
}
|
|
|
|
if (ah->ah_version != AR5K_AR5210) {
|
|
|
|
/* ...update PLL if needed */
|
|
if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
|
|
ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
|
|
udelay(300);
|
|
}
|
|
|
|
/* ...set the PHY operating mode */
|
|
ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
|
|
ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/**************************************\
|
|
* Post-initvals register modifications *
|
|
\**************************************/
|
|
|
|
/* TODO: Half/Quarter rate */
|
|
static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
|
|
struct ieee80211_channel *channel)
|
|
{
|
|
if (ah->ah_version == AR5K_AR5212 &&
|
|
ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
|
|
|
|
/* Setup ADC control */
|
|
ath5k_hw_reg_write(ah,
|
|
(AR5K_REG_SM(2,
|
|
AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
|
|
AR5K_REG_SM(2,
|
|
AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
|
|
AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
|
|
AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
|
|
AR5K_PHY_ADC_CTL);
|
|
|
|
|
|
|
|
/* Disable barker RSSI threshold */
|
|
AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
|
|
AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
|
|
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
|
|
AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
|
|
|
|
/* Set the mute mask */
|
|
ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
|
|
}
|
|
|
|
/* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
|
|
if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
|
|
ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
|
|
|
|
/* Enable DCU double buffering */
|
|
if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
|
|
AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
|
|
AR5K_TXCFG_DCU_DBL_BUF_DIS);
|
|
|
|
/* Set DAC/ADC delays */
|
|
if (ah->ah_version == AR5K_AR5212) {
|
|
u32 scal;
|
|
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
|
|
if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
|
|
scal = AR5K_PHY_SCAL_32MHZ_2417;
|
|
else if (ee->ee_is_hb63)
|
|
scal = AR5K_PHY_SCAL_32MHZ_HB63;
|
|
else
|
|
scal = AR5K_PHY_SCAL_32MHZ;
|
|
ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
|
|
}
|
|
|
|
/* Set fast ADC */
|
|
if ((ah->ah_radio == AR5K_RF5413) ||
|
|
(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
|
|
u32 fast_adc = true;
|
|
|
|
if (channel->center_freq == 2462 ||
|
|
channel->center_freq == 2467)
|
|
fast_adc = 0;
|
|
|
|
/* Only update if needed */
|
|
if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
|
|
ath5k_hw_reg_write(ah, fast_adc,
|
|
AR5K_PHY_FAST_ADC);
|
|
}
|
|
|
|
/* Fix for first revision of the RF5112 RF chipset */
|
|
if (ah->ah_radio == AR5K_RF5112 &&
|
|
ah->ah_radio_5ghz_revision <
|
|
AR5K_SREV_RAD_5112A) {
|
|
u32 data;
|
|
ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
|
|
AR5K_PHY_CCKTXCTL);
|
|
if (channel->hw_value & CHANNEL_5GHZ)
|
|
data = 0xffb81020;
|
|
else
|
|
data = 0xffb80d20;
|
|
ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
|
|
}
|
|
|
|
if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
|
|
/* Clear QCU/DCU clock gating register */
|
|
ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
|
|
/* Set DAC/ADC delays */
|
|
ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
|
|
AR5K_PHY_SCAL);
|
|
/* Enable PCU FIFO corruption ECO */
|
|
AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
|
|
AR5K_DIAG_SW_ECO_ENABLE);
|
|
}
|
|
}
|
|
|
|
static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
|
|
struct ieee80211_channel *channel, u8 ee_mode)
|
|
{
|
|
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
|
|
s16 cck_ofdm_pwr_delta;
|
|
|
|
/* TODO: Add support for AR5210 EEPROM */
|
|
if (ah->ah_version == AR5K_AR5210)
|
|
return;
|
|
|
|
/* Adjust power delta for channel 14 */
|
|
if (channel->center_freq == 2484)
|
|
cck_ofdm_pwr_delta =
|
|
((ee->ee_cck_ofdm_power_delta -
|
|
ee->ee_scaled_cck_delta) * 2) / 10;
|
|
else
|
|
cck_ofdm_pwr_delta =
|
|
(ee->ee_cck_ofdm_power_delta * 2) / 10;
|
|
|
|
/* Set CCK to OFDM power delta on tx power
|
|
* adjustment register */
|
|
if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
|
|
if (channel->hw_value == CHANNEL_G)
|
|
ath5k_hw_reg_write(ah,
|
|
AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
|
|
AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
|
|
AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
|
|
AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
|
|
AR5K_PHY_TX_PWR_ADJ);
|
|
else
|
|
ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
|
|
} else {
|
|
/* For older revs we scale power on sw during tx power
|
|
* setup */
|
|
ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
|
|
ah->ah_txpower.txp_cck_ofdm_gainf_delta =
|
|
ee->ee_cck_ofdm_gain_delta;
|
|
}
|
|
|
|
/* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
|
|
* too */
|
|
ath5k_hw_set_antenna_switch(ah, ee_mode);
|
|
|
|
/* Noise floor threshold */
|
|
ath5k_hw_reg_write(ah,
|
|
AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
|
|
AR5K_PHY_NFTHRES);
|
|
|
|
if ((channel->hw_value & CHANNEL_TURBO) &&
|
|
(ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
|
|
/* Switch settling time (Turbo) */
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
|
|
AR5K_PHY_SETTLING_SWITCH,
|
|
ee->ee_switch_settling_turbo[ee_mode]);
|
|
|
|
/* Tx/Rx attenuation (Turbo) */
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
|
|
AR5K_PHY_GAIN_TXRX_ATTEN,
|
|
ee->ee_atn_tx_rx_turbo[ee_mode]);
|
|
|
|
/* ADC/PGA desired size (Turbo) */
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
|
|
AR5K_PHY_DESIRED_SIZE_ADC,
|
|
ee->ee_adc_desired_size_turbo[ee_mode]);
|
|
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
|
|
AR5K_PHY_DESIRED_SIZE_PGA,
|
|
ee->ee_pga_desired_size_turbo[ee_mode]);
|
|
|
|
/* Tx/Rx margin (Turbo) */
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
|
|
AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
|
|
ee->ee_margin_tx_rx_turbo[ee_mode]);
|
|
|
|
} else {
|
|
/* Switch settling time */
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
|
|
AR5K_PHY_SETTLING_SWITCH,
|
|
ee->ee_switch_settling[ee_mode]);
|
|
|
|
/* Tx/Rx attenuation */
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
|
|
AR5K_PHY_GAIN_TXRX_ATTEN,
|
|
ee->ee_atn_tx_rx[ee_mode]);
|
|
|
|
/* ADC/PGA desired size */
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
|
|
AR5K_PHY_DESIRED_SIZE_ADC,
|
|
ee->ee_adc_desired_size[ee_mode]);
|
|
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
|
|
AR5K_PHY_DESIRED_SIZE_PGA,
|
|
ee->ee_pga_desired_size[ee_mode]);
|
|
|
|
/* Tx/Rx margin */
|
|
if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
|
|
AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
|
|
ee->ee_margin_tx_rx[ee_mode]);
|
|
}
|
|
|
|
/* XPA delays */
|
|
ath5k_hw_reg_write(ah,
|
|
(ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
|
|
(ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
|
|
(ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
|
|
(ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
|
|
|
|
/* XLNA delay */
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
|
|
AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
|
|
ee->ee_tx_end2xlna_enable[ee_mode]);
|
|
|
|
/* Thresh64 (ANI) */
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
|
|
AR5K_PHY_NF_THRESH62,
|
|
ee->ee_thr_62[ee_mode]);
|
|
|
|
/* False detect backoff for channels
|
|
* that have spur noise. Write the new
|
|
* cyclic power RSSI threshold. */
|
|
if (ath5k_hw_chan_has_spur_noise(ah, channel))
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
|
|
AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
|
|
AR5K_INIT_CYCRSSI_THR1 +
|
|
ee->ee_false_detect[ee_mode]);
|
|
else
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
|
|
AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
|
|
AR5K_INIT_CYCRSSI_THR1);
|
|
|
|
/* I/Q correction (set enable bit last to match HAL sources) */
|
|
/* TODO: Per channel i/q infos ? */
|
|
if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
|
|
ee->ee_i_cal[ee_mode]);
|
|
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
|
|
ee->ee_q_cal[ee_mode]);
|
|
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
|
|
}
|
|
|
|
/* Heavy clipping -disable for now */
|
|
if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
|
|
ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
|
|
}
|
|
|
|
|
|
/*********************\
|
|
* Main reset function *
|
|
\*********************/
|
|
|
|
int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
|
|
struct ieee80211_channel *channel, bool change_channel)
|
|
{
|
|
struct ath_common *common = ath5k_hw_common(ah);
|
|
u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo;
|
|
u8 mode, freq, ee_mode;
|
|
int i, ret;
|
|
|
|
ee_mode = 0;
|
|
staid1_flags = 0;
|
|
tsf_up = 0;
|
|
tsf_lo = 0;
|
|
freq = 0;
|
|
mode = 0;
|
|
|
|
|
|
/*
|
|
* Stop PCU
|
|
*/
|
|
ath5k_hw_stop_rx_pcu(ah);
|
|
|
|
/*
|
|
* Stop DMA
|
|
*
|
|
* Note: If DMA didn't stop continue
|
|
* since only a reset will fix it.
|
|
*/
|
|
ath5k_hw_dma_stop(ah);
|
|
|
|
/*
|
|
* Save some registers before a reset
|
|
*/
|
|
/*DCU/Antenna selection not available on 5210*/
|
|
if (ah->ah_version != AR5K_AR5210) {
|
|
|
|
switch (channel->hw_value & CHANNEL_MODES) {
|
|
case CHANNEL_A:
|
|
mode = AR5K_MODE_11A;
|
|
freq = AR5K_INI_RFGAIN_5GHZ;
|
|
ee_mode = AR5K_EEPROM_MODE_11A;
|
|
break;
|
|
case CHANNEL_G:
|
|
mode = AR5K_MODE_11G;
|
|
freq = AR5K_INI_RFGAIN_2GHZ;
|
|
ee_mode = AR5K_EEPROM_MODE_11G;
|
|
break;
|
|
case CHANNEL_B:
|
|
mode = AR5K_MODE_11B;
|
|
freq = AR5K_INI_RFGAIN_2GHZ;
|
|
ee_mode = AR5K_EEPROM_MODE_11B;
|
|
break;
|
|
case CHANNEL_T:
|
|
mode = AR5K_MODE_11A_TURBO;
|
|
freq = AR5K_INI_RFGAIN_5GHZ;
|
|
ee_mode = AR5K_EEPROM_MODE_11A;
|
|
break;
|
|
case CHANNEL_TG:
|
|
if (ah->ah_version == AR5K_AR5211) {
|
|
ATH5K_ERR(ah->ah_sc,
|
|
"TurboG mode not available on 5211");
|
|
return -EINVAL;
|
|
}
|
|
mode = AR5K_MODE_11G_TURBO;
|
|
freq = AR5K_INI_RFGAIN_2GHZ;
|
|
ee_mode = AR5K_EEPROM_MODE_11G;
|
|
break;
|
|
case CHANNEL_XR:
|
|
if (ah->ah_version == AR5K_AR5211) {
|
|
ATH5K_ERR(ah->ah_sc,
|
|
"XR mode not available on 5211");
|
|
return -EINVAL;
|
|
}
|
|
mode = AR5K_MODE_XR;
|
|
freq = AR5K_INI_RFGAIN_5GHZ;
|
|
ee_mode = AR5K_EEPROM_MODE_11A;
|
|
break;
|
|
default:
|
|
ATH5K_ERR(ah->ah_sc,
|
|
"invalid channel: %d\n", channel->center_freq);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (change_channel) {
|
|
/*
|
|
* Save frame sequence count
|
|
* For revs. after Oahu, only save
|
|
* seq num for DCU 0 (Global seq num)
|
|
*/
|
|
if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
|
|
|
|
for (i = 0; i < 10; i++)
|
|
s_seq[i] = ath5k_hw_reg_read(ah,
|
|
AR5K_QUEUE_DCU_SEQNUM(i));
|
|
|
|
} else {
|
|
s_seq[0] = ath5k_hw_reg_read(ah,
|
|
AR5K_QUEUE_DCU_SEQNUM(0));
|
|
}
|
|
|
|
/* TSF accelerates on AR5211 during reset
|
|
* As a workaround save it here and restore
|
|
* it later so that it's back in time after
|
|
* reset. This way it'll get re-synced on the
|
|
* next beacon without breaking ad-hoc.
|
|
*
|
|
* On AR5212 TSF is almost preserved across a
|
|
* reset so it stays back in time anyway and
|
|
* we don't have to save/restore it.
|
|
*
|
|
* XXX: Since this breaks power saving we have
|
|
* to disable power saving until we receive the
|
|
* next beacon, so we can resync beacon timers */
|
|
if (ah->ah_version == AR5K_AR5211) {
|
|
tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
|
|
tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
|
|
}
|
|
}
|
|
|
|
if (ah->ah_version == AR5K_AR5212) {
|
|
/* Restore normal 32/40MHz clock operation
|
|
* to avoid register access delay on certain
|
|
* PHY registers */
|
|
ath5k_hw_set_sleep_clock(ah, false);
|
|
|
|
/* Since we are going to write rf buffer
|
|
* check if we have any pending gain_F
|
|
* optimization settings */
|
|
if (change_channel && ah->ah_rf_banks != NULL)
|
|
ath5k_hw_gainf_calibrate(ah);
|
|
}
|
|
}
|
|
|
|
/*GPIOs*/
|
|
s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
|
|
AR5K_PCICFG_LEDSTATE;
|
|
s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
|
|
s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
|
|
|
|
/* AR5K_STA_ID1 flags, only preserve antenna
|
|
* settings and ack/cts rate mode */
|
|
staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
|
|
(AR5K_STA_ID1_DEFAULT_ANTENNA |
|
|
AR5K_STA_ID1_DESC_ANTENNA |
|
|
AR5K_STA_ID1_RTS_DEF_ANTENNA |
|
|
AR5K_STA_ID1_ACKCTS_6MB |
|
|
AR5K_STA_ID1_BASE_RATE_11B |
|
|
AR5K_STA_ID1_SELFGEN_DEF_ANT);
|
|
|
|
/* Wakeup the device */
|
|
ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* PHY access enable */
|
|
if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
|
|
ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
|
|
else
|
|
ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
|
|
AR5K_PHY(0));
|
|
|
|
/* Write initial settings */
|
|
ret = ath5k_hw_write_initvals(ah, mode, change_channel);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Initialize core clock settings */
|
|
ath5k_hw_init_core_clock(ah);
|
|
|
|
/*
|
|
* Tweak initval settings for revised
|
|
* chipsets and add some more config
|
|
* bits
|
|
*/
|
|
ath5k_hw_tweak_initval_settings(ah, channel);
|
|
|
|
/* Commit values from EEPROM */
|
|
ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode);
|
|
|
|
|
|
/*
|
|
* Restore saved values
|
|
*/
|
|
|
|
/*DCU/Antenna selection not available on 5210*/
|
|
if (ah->ah_version != AR5K_AR5210) {
|
|
|
|
if (change_channel) {
|
|
if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
|
|
for (i = 0; i < 10; i++)
|
|
ath5k_hw_reg_write(ah, s_seq[i],
|
|
AR5K_QUEUE_DCU_SEQNUM(i));
|
|
} else {
|
|
ath5k_hw_reg_write(ah, s_seq[0],
|
|
AR5K_QUEUE_DCU_SEQNUM(0));
|
|
}
|
|
|
|
|
|
if (ah->ah_version == AR5K_AR5211) {
|
|
ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
|
|
ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Ledstate */
|
|
AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
|
|
|
|
/* Gpio settings */
|
|
ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
|
|
ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
|
|
|
|
/* Restore sta_id flags and preserve our mac address*/
|
|
ath5k_hw_reg_write(ah,
|
|
get_unaligned_le32(common->macaddr),
|
|
AR5K_STA_ID0);
|
|
ath5k_hw_reg_write(ah,
|
|
staid1_flags | get_unaligned_le16(common->macaddr + 4),
|
|
AR5K_STA_ID1);
|
|
|
|
|
|
/*
|
|
* Initialize PCU
|
|
*/
|
|
ath5k_hw_pcu_init(ah, op_mode, mode);
|
|
|
|
/*
|
|
* Initialize PHY
|
|
*/
|
|
ret = ath5k_hw_phy_init(ah, channel, mode, ee_mode, freq);
|
|
if (ret) {
|
|
ATH5K_ERR(ah->ah_sc,
|
|
"failed to initialize PHY (%i) !\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Configure QCUs/DCUs
|
|
*/
|
|
ret = ath5k_hw_init_queues(ah);
|
|
if (ret)
|
|
return ret;
|
|
|
|
|
|
/*
|
|
* Initialize DMA/Interrupts
|
|
*/
|
|
ath5k_hw_dma_init(ah);
|
|
|
|
|
|
/* Enable 32KHz clock function for AR5212+ chips
|
|
* Set clocks to 32KHz operation and use an
|
|
* external 32KHz crystal when sleeping if one
|
|
* exists */
|
|
if (ah->ah_version == AR5K_AR5212 &&
|
|
op_mode != NL80211_IFTYPE_AP)
|
|
ath5k_hw_set_sleep_clock(ah, true);
|
|
|
|
/*
|
|
* Disable beacons and reset the TSF
|
|
*/
|
|
AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
|
|
ath5k_hw_reset_tsf(ah);
|
|
return 0;
|
|
}
|